1. Power MOSFET
Pranjal Barman

2. Power MOSFET • Introduction Advantages and Applications
Outline
• Introduction
Advantages and Applications
Construction of power MOSFET
• Physical operations of MOSFETs
• Power MOSFET Characteristics
• Factors limiting operating specifications of MOSFETs
• Improved Designs
• Future of power MOSFET

3. Introduction
A power MOSFET is a specific type of metal oxide semiconductor field-effect transistor designed to handle significant power levels.
It was made possible by the evolution of CMOS technology, developed for manufacturing Integrated Circuits in the late 1970s.
The power MOSFET shares its operating principle with its low-power counterpart, the lateral MOSFET.

4. Advantages High speed switching High input impedance
High ON-state current handling capability
High OFF-state blocking voltage
Higher breakdown voltage

5. Applications

6. Construction of power VDMOSFET
Planar-gate structure
P-base region and the N+ source regions are self-aligned to the edge of the polysilicon gate
Thick N-drift region
N+ substrate act as a drain

7. Physics of MOSFET Insulator with finite resistivity
Charge only in the metal and semiconductor
Work functions of metal and semiconductor are same

8. Accumulation
Excess minority carriers produced at the surface

9. Depletion

10. Inversion

11. Total charge in semiconductor

12. Charge,Field and Potential distribution

13. Graded doping profile

14. MOSFET characteristics
𝑉 𝑔𝑠 < 𝑉 𝑡ℎ ,cut off
𝑉 𝑔𝑠 - 𝑉 𝑡ℎ = 𝑉 𝑑𝑠 saturation
𝑉 𝑔𝑠 - 𝑉 𝑡ℎ < 𝑉 𝑑𝑠 ,pinch off
K depends on temperature and device geometry

15. Transconductance
High transconductance is desirable to handle large current with low gate drive voltage
Mobility degradation with temperature affect the transconductance
Define the gain of the MOSFET

16. Drift Velocity Saturation

17. Effect of parasitic BJT
Transistor should not be turned on
Shorted body and source
A parasitic diode formed between source and drain

18. Third quadrant operation
Current flow reverse direction compared to first quadrant
No current saturation behavior observed
Most common in DC-DC buck converters

19. Field profile of VDMOSFET

20. MOS capacitances Non linear and depends on device geometry
Gate-source capacitance Cgs approximately constant and independent of applied voltages.
Gate-drain capacitance Cgd varies with applied voltage variation due to growth of depletion layer thickness until inversion layer is formed.
Cds does not materially effect switching characteristics

21. VDMOS capacitances

22. Variation of capacitance with bias

23. Factors limiting operating specifications
Maximum gate to source voltage
MOSFET breakdown voltage
MOSFET ON-state losses
MOSFET Safe Operating Area (SOA)

24. Maximum gate-source voltage
• VGS(max) = maximum permissible gate- source voltage. • If VGS >VGS(max) rupture of gate oxide by large electric fields possible. • EBD(oxide) ≈ 5-10 million V/cm • Gate oxide typically 1000 A thick • VGS(max) < 50 V • Typical VGS(max) V • Static charge on gate conductor can rupture gate oxide

25. MOSFET breakdown Caused by avalanche breakdown of drain body junction
Larger value of breakdown could be achieved by
Avoidance of drain-source reach-through by heavy doping of body and light doping of drain drift region
Appropriate length of drain drift region
Field plate action of gate conductor overlap of drain region
Prevent turn-on of parasitic BJT with body-source short

26. ON state loss On-state power dissipation 𝑃 𝑜𝑛 = 𝐼 𝐷 2 . 𝑅 𝑑𝑠 (on)
𝑅 𝑑𝑠 = 𝑅 𝑐𝑠 + 𝑅 𝑛+ + 𝑅 𝑐ℎ + 𝑅 𝑎 + 𝑅 𝑗𝑓𝑒𝑡 + 𝑅 𝑑 + 𝑅 𝑠𝑢𝑏 + 𝑅 𝑐𝑑
Large 𝑉 𝑔𝑠 minimizes accumulation layer resistance and channel resistance 
𝑅 𝑑𝑠 (on) dominated by drain drift resistance for BVdss > few 100 V
𝑅 𝑑𝑠 (on) increases as temperature increses. Due to decrease in carrier mobility with increasing temperature.

27. ON state resistances Channel resistance Accumulation resistance
JFET resistance
Drift resistance
Substrate resistance

28. Safe Operating Area Three factors determine SOA
Maximum drain current Idm
Internal junction temperature Tj which is governed by power dissipation
Breakdown voltage BVdss

29. Improved Design Approach
Reduce specific ON resistance
Shorter channel length
Improve input capacitance
Higher reverse blocking capability

30. UMOSFET Specific resistance is substantially small
Trench gate architecture
Does not contain JFET region
High input capacitance
High gate transfer charge
Complex fabrication process

31. U-MOSFET with rounded trench and thicker oxide

32. ON resistance

33. Shielded Channel MOSFET
Shielding junction unique JFET region
Reduced fabrication complexity
Shorter channel length
Reduced specific on resistance
Reduced input capacitance
Reduced gate transfer charge

34. Shielded Channel MOSFET

35. Charge Couple MOSFET Two dimensional charge coupling effect
Electrode embedded within oxide coated deep trenches
Higher doping drift region
Significantly smaller specific ON resistance
Large input and gate transfer capacitance

36. Charge Couple MOSFET

37. CC-MOSFET with source electrode
Presence of the gate electrode within the deep trenches adjacent to the drift region increases the capacitance and gate charge degrading the switching performance of the power CC-MOSFET structure. This problem can be overcome by using a source connected electrode in the trenches adjacent to the drift region.

38. CCMOS ON resistance No JFET resistance
Drift resistance is parallel to accumulation resistance

39. Super Junction MOSFET Large blocking voltage capability upto 1200V
Alternating P and N type drift region
Two dimensional charge coupling
Highly doped drift reduce ON resistance

40. Super Junction MOSFET

41. ON resistance comparison
MOSFET
Gate voltage=4.5V
(mohm-cm2)
Gate voltage=10V
VDMOS
1.405
0.704
UMOS
0.613
0.176
SCMOS
0.235
0.202
CCMOS
0.380
0.017
SJMOS
0.911
0.839

42. Wide Band Semiconductor
Si devices are limited to operate at junction temperature of 200 degree centigrade
Si power devices not suitable for high frequency
Lower specific on resistance of WB material
SiC/GaN offer the potential to overcome the limitations of Si

43. Silicon Carbide MOSFET
Specific ON resistance could be reduced by wide band gap semiconductor
Quality of the interface between the thermally grown oxide and the SiC surface has been poor resulting in low inversion layer mobility
High electric field within the gate oxide leading to its rupture during operation
Two types of design approach-inversion and accumulation

44. Silicon Carbide Inversion MOSFET
Larger threshold required to make inversion
P-base doping should be very low to achieve small threshold
High electric field rupture gate oxide
Shielding allows to reduce channel length

45. Inversion mode SiC-MOSFET

46. SiC Accumulation MOSFET
A lightly doped N-base region used instead of P-base region
Positive bias to the N-base region form accumulation region
Prevent large electric field by P+ shielding
Lower threshold voltage
Shorter channel length

47. Field pattern

48. SiC-MOS Comparison Inversion Accumulation Higher Threshold
Low channel mobility
High specific ON resistance
Lower Threshold
High channel mobility
Low specific ON resistance

49. Future of power MOSFET
SiC MOS could outperform the blocking voltage upto 10000V
IGBT favored due to low on-state voltage drop
Very low specific on resistance with UMOSFET
Silicon power integrated circuits

50. References Advanced power MOSFET-J.Baliga
Power electronics converter application and design-N.Mohan
Fundamental of power semiconductor device-J.Baliga
Power MOSFETS basic-A.Sattar
The future of power semiconductor device-J. Baliga

51. Thank you