1. CHAPTER 6: MOSFET & RELATED DEVICES CHAPTER 6: MOSFET & RELATED DEVICES Part 1

2. MOSFET and Related Devices 6.1 The MOS diode 6.2 MOSFET fundamentals 6.3 MOSFET scaling 6.4 CMOS and BiCMOS 6.5 MOSFET on insulator 6.6 MOS memory structures 6.7 The power MOSFET

3. THE MOS DIODES Figure 6.1. (a) Perspective view of a metal-oxide-semiconductor (MOS) diode. (b) Cross-section of an MOS diode.

5. Figure 6.2. Energy band diagram of an ideal MOS diode at V = 0. THE MOS DIODES (cont.)

7. KEYWORDS : a)Work Function, : Energy difference between the Fermi level and the vacuum level. b) Electron affinity, : Energy difference between the conduction band edge and the vacuum level in the semiconductor. c) : Energy difference between the Fermi level E F and the intrinsic Fermi level E i

8. An ideal MOS is defined as follows: a)At zero applied bias, the energy difference between the metal work function (q  m ) and the semiconductor work function (q  s ) is zero or the work function difference (q  ms ) is zero # The energy band is flat (flat band condition) when there is no applied voltage b) The only charges that exist in the diode under any biasing conditions are those in the semiconductor and those with equal but opposite sign on the metal surface adjacent to the oxide. c) There is no carrier transport through the oxide under direct current (dc) - biasing condition or the resistivity of the oxide is infinite. (1) THE MOS DIODES (cont.)

9. a)ACCUMULATION CASE : -V<0 is applied to the metal plate, holes will be induced at the SiO 2 – Si interface. -Bands near the semiconductor surface are bent upward. It cause an increase in the energy E i -E F which in turn gives rise to an enhanced concentration and accumulation of holes near the oxide- semiconductor interface -No current flows. b) DEPLETION CASE : -V>0 is applied, the energy bands near the semiconductor surface are bent downward. -Holes (majority carriers) are depleted. THE MOS DIODES CASES (cont.) ENERGY BAND DIAGRAMS AND CHARGE DISTRIBUTIONS OF AN IDEAL MOS DIODE

10. c) INVERSION CASE :  Larger positive voltage applied, energy bands bend downward even more so the E i at the surface crosses over the Fermi level.  The positive gate voltage starts to induce excess electrons at the SiO 2 – Si interface.  Electrons greater than holes, thus the surface is inverted. THE MOS DIODES (cont.) Carrier density (holes) depends on energy difference

11. Figure 6.4. Energy band diagrams at the surface of a p-type semiconductor. The surface depletion region THE MOS DIODES (cont.)

12.  (electrostatic potential)=0 (in bulk)  s (surface potential)=  (at s/c surface) Electron concentration Hole concentration (2) (3) Expressed as a function of  See eq. (4) & (5) (4) (5)  is positive when the band is bent downward (6) (7) Densities at the surface

13. The following regions of surface potential can be distinguished:  s  0Accumulation of holes (bands bend upward)  s =0Flat-band condition  B  s  0Depletion of holes (bands bend downward)  s =  B Midgap with n s = n p = n i (intrinsic concen.)  s >  B Inversion (bands bend downward) (7)  as a function of distance (1D poisons eq.)  s (x): charge density per unit volume  s : dielectric permittivity

14. When the semiconductor is depleted to a width of W and the charge within the semiconductor is given by, (8) (9) Maximum width of the surface depletion region W m : Note: Potential distribution = one sided n + -p junction The surface is inverted whenever  s  B n s (e concen. at surface)= n A (substrate impurity concentration) (10) Electrostatic potential at surface depletion region:

15. Figure 6.5. Maximum depletion-layer width versus impurity concentration of Si and GaAs under strong-inversion condition. Example For an ideal metal-SiO 2 -Si diode having N A =10 17 cm -3, calculate the maximum width of the surface depletion region Solution: At room temp. kT/q=0.026 and n i =9.65x10 9 cm -3, the dielectric permittivity of Si is 11.9 x 8.85 x 10 -14 F/cm

16. No work function differences – applied voltage appear partly across oxide & across semiconductor Potential across the oxide Field in the oxide Charge per unit area Oxide capacitance per unit area VoVo oo QSQS CoCo Ideal MOS Curves (a) Band diagram of an ideal MOS diode. (b) Charge distributions under inversion condition. (c) Electric field distribution. (d) Potential distribution

17. C Total capacitance of MOS diode C o Oxide capacitance C j Semiconductor depletion-layer capacitance W Width of depletion  o Permittivity in vacuum  ox Insulator permittivity (a) High-frequency MOS C-V curve showing its approximated segments (dashed lines). Inset shows the series connection of the capacitors. (b) Effect of frequency on the C-V curve. 2 Threshold voltage: Minimum value of total capacitance:

18. The SiO 2 – Si MOS diode  Metal-SiO 2 -Si : most extensively studied  Work function difference q  ms  0 (for metal electrodes)  Work function semiconductor q  s (Energy difference: Between vacuum level – Fermi level)  Work function metal q  m  difference : q  ms  (q  ms - q  s )  Aluminum : q  m = 4.1eV  Polysilicon : n+ q  m = 4.05eV p+ q  m = 5.05eV Work function difference as a function of background impurity concentration for Al, n+-, and p+ polysilicon gate materials.

19. (a) Energy band diagram of an isolated metal and an isolated semiconductor with an oxide layer between them. (b) Energy band diagram of an MOS diode in thermal equilibrium.  To construct energy band diagram (in the figure)  In the isolated metal & semiconductor – all bands are flat  At thermal equilibrium: constant Fermi level & continuous vacuum level.  At thermal equilibrium:  metal  +ve charge  semiconductor surface  –ve charge  To get ideal flat band: apply a voltage = q  ms  So apply –ve voltage V FB to metal  flat band voltage ( V FB =  ms )

20. Interface Traps & Oxide Charges  MOS diode is affected by charges in the oxide & traps in the SiO 2 -Si interface  Classifications of traps & charges:  Interface-trapped charge  Fixed oxide charge  Oxide trapped charge  Mobile ionic charge  Interface trapped charge Q it  due to SiO 2 -Si interface properties & chemical composition in the interface  Location: SiO 2 -Si  Interface trap density (number of interface traps per unit area & per eV)  in  100  the interface trap density is an order of magnitude smaller than  111 

21.  Oxide-trapped charges, Q ot  Associated with defects in SiO 2  The charges can be created (Eg. by X-ray radiation or high energy electron bombardment) – traps are distributed inside the oxide layer.  Can be removed by low temperature annealing  Mobile ionic charges, Q m  Eg. Sodium & alkali ions – mobile under raised-temperature (Eg. >100 o C) & high field operations.  Stability problem in semiconductor devices operated under high bias & high temperature conditions  Mobile ion charges move back & forth through the oxide layer  cause shifts of CV curves along voltage axis  Mobile ions have to be eliminated Fixed charge, Q f  Location: within 3nm of the SiO 2 -Si interface  The charge is fixed – cannot be charged or discharged  Q f is generally +ve & can be regarded as a charge sheet located at the SiO 2 -Si interface

22. Effect of a sheet charge within the oxide. (a) Condition for V G = 0. (b) Flat-band condition.  Evaluate the effective net charges per unit area (C/cm 2 ) on the flat band voltage  Consider a +ve sheet charge per unit area Q o within the oxide  induce –ve charges (partly in metal, partly in semicond.) (fig. (a))  Resulting field distribution  assumed that there is no work function difference ( q  ms =0 )  To reach a flat band condition (no charge induced)  apply –ve voltage to metal (fig. (b))  As –ve voltage increases  more –ve charges on the metal  electric field distribution shift downward until the electric field is zero (at surface)  Area contained under the electric field distribution corresponds to the flat-band voltage V FB :

23. Q o Density of the sheet charge x o Location within the oxide  When sheet charge very close to metal  if x o =0 : induce no charges, no effect on the flat band voltage  When Q o very close to semiconductor  x o = d : it will exert its max influence, give rise to a flat band voltage:  Arbitrary space charge distribution within the oxide:  (x) : volume charge density in the oxide  ot (x) : volume charge density for oxide-trapped charges  m (x) : volume charge density for mobile ionic charges If q  ms  0 & interface-trapped charges is negligible  experimental C-V curve will be shifted from the ideal theoretical curve by an amount : Important!

24. Effect of a fixed oxide charge and interface traps on the C-V characteristics of an MOS diode.