Analytical Delay and Variation Modeling for Subthreshold Circuits Sungil Kim and Vishwani D. Agrawal, Ph.D. Auburn University Department of Electrical and Computer Engineering {szk0075, agrawvd}@auburn.edu 4/9/2016

Table of Contents I. Background Constraint on power for modern electronics Using subthreshold region to achieve ultra-low-power II. Analytical Delay Model Review of Alpha-power MOSFET model Proposed variations-aware delay model III. Variations Models Proposed PVT (process, voltage, temp) variations models Comparison with previous research 2

Constraint on Power in Modern Electronics Ultra Small Computer / Imager Biomedical Sensor /Monitoring Device Portable / Wearable Device Low power electronics are common as shown in three examples here. While some electronics like super computer requires high performance, others whose primary concern is low power consumption operates at low to moderate speed: MHz range to lo low GHz ranges. Therefore, here, we focus on power consumption and management and methods to minimize energy and associated problems with proposed design. For Low to Moderate Speed Systems: Power Consumption / Management >>> Performance 3

Subthreshold: Scaling Down VDD Below Vth Idea of Subthreshold Circuits: 1971 (Meindl and Swanson) Workability: 1900s – 2000s (Chandrakasan, Blaauw, Sylvester…) PTM 16-nm LP Vth = 0.68V Drawback: PVT Variations - Process - Voltage - Temperature Minimum Energy 4

Necessity of Delay Model and Challenges Accurate delay model => better predict circuit behavior Set the operating region and process corners — essential for extreme environments — military applications (extreme temperature) Used for timing analysis and VLSI design stage Subthreshold Circuits pose challenges — susceptible to PVT (process, voltage, temp) variations — Isat exponentially depends on gate, threshold voltage — reduced Ion / Ioff => Alpha-power model is no longer accurate New delay model for the subthreshold is needed. 5

Review of Alpha-Power MOSFET Model T. Sakurai and A. Richard Newton mobility degradation at high electric fields // alpha is a carrier velocity saturation index. α = carrier velocity saturation index Mobility degrades at high electric fields Alpha-Power MOSFET Model are susceptible to PVT variations 6

Proposed Subthreshold Delay Model 0 —> 1 Input The delay of a logic gate can then be estimated as the time taken to charge and discharge the output node through the PMOS/NMOS transistor 7

Simulation Results PTM 16-nm LP Error Alpha-power (red) Proposed (green) Average 39.8% 16.5% Worst 71.1% 33.4% 8

Proposed Voltage Variation Model Delay exponentially depends on supply voltage difference Compensated by VDD2 / VDD1 9

Proposed Model Result (1): VDD Variation PTM 16-nm LP Avg. Error = 14.6%, Max. Error = 79.1% 10

Proposed Temperature Variation Model BSIM54 model: u = carrier mobility / Temperature increase => u and Vth decreases. Kth = temperature coefficient for vth UTE around -1.5. Compensation Factor of (T1 / T2)2 11

Proposed Model Result (2): Temp Variation Avg. Error = 6.8%, Max. Error = 37.9% PTM 16-nm LP 12

Proposed Process Variation Model Mainly due to threshold voltage (Vth) variation Other factors: effective channel length, doping concentration Delay exponentially depends on threshold voltage difference 13

Proposed Model Result (3): Vth Variation PTM 16-nm LP Monte Carlo 1000 runs Avg. Error = 1%, Max. Error = 6% 14

Effect of Compensation Factor Carefully chosen from the results of previous research Error VDD Variation Temp Variation without with factor Average 27.4% 14.6% 62.1% 6.8% Best 0.4% 0.1% 20.2% Worst 131.7% 79.1% 87.5% 37.9% T. Lin, K.-S. Chong, B.-H. Gwee, J. S. Chang, and Z.-X. Qiu, “Analytical delay variation modelling for evaluating sub-threshold synchronous/asynchronous designs,” in Proc. IEEE Int. NEWCAS, Jun. 20–23, 2010, pp. 69–72. 20

Summary Delay Model Variations Model Verify alpha-power MOSFET model in the subthrehsold region Proposed and verified analytical delay model Variations Model Adding compensation factors to increase the accuracy Simulate the proposed models over broader ranges of VDD Verify on smaller technology node (16-nm) that have more variations than 130-nm or 45-nm models 15

Questions? Thank you!