USART Universal Synchronous Asynchronous Receiver Transmitter Serial Communications Interface

How it Works: Transmission

How it Works: Transmission

How it Works: Transmission 1 start bit 8 (or 9) data bits 1 stop bit No parity bit lsb to msb

How it Works: Reception RCREG is actually a two-deep queue. It can be read from twice. So you can receive two bytes of data before needing to read.

How it Works: Reception

How it Works: Reception The data on the RB1/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or allow level is present at the RX pin.

How it Works: Baud Rates BRGH = TXSTA,2 SPBRG = 99h (BANK 1!) Fosc = Frequency of Oscillation = 4 Mhz = 4000000 Taken from: http://www.microcontrollerboard.com/pic_serial_communication.html

A Chart! BRGH = 1

Assignment 2, but Easier!

TX and RX Pins B1 is RX B2 is TX bsf STATUS,RP0 movlw b'10000110' movwf TRISB Set TRISB pins 1 and 2 to 1 (even though we are transmitting).

Baud Rate Generator setBaudRate bsf TXSTA,BRGH ; Select high baud rate movlw d'25' movwf SPBRG ; 9600 baud TXSTA and SPBRG are in bank 1! BRGH – Baud Rate Mode 1 = high baud rate 0 = low baud rate

Enable Asynchronous Communication configureModes bcf TXSTA,SYNC ; selects Async mode bcf STATUS,RP0 ; return to bank 0 bsf RCSTA,SPEN TXSTA is in bank 1! Clear bit sync to enable async mode Set bit SPEN to enable PORTB pins 1 and 2 as serial port pins. bcf TXSTA,SYNC ; selects Async mode

Transmit Chip bsf TXSTA,TXEN Enables transmission. Sets the output line high.

Transmit Chip movlw d'7' movwf TXREG bsf STATUS,RP0 waitUntilDone btfss TXSTA,TRMT goto waitUntilDone As soon as TXREG is loaded with data, transmission will be enabled. TSR (Transmit Shift Register) will be loaded with data from TXREG and send data out of TX Once transmission is complete, bit TRMT is set. TRMT is cleared when data is put back into TSR.

Receive Chip bsf RCSTA,CREN Tells the USART to start listening on the RX pin. The RX line must be high before you start listening to it. Otherwise it will immediately start reading data and weird stuff will happen.

Receive Chip waitForData btfss PIR1,RCIF goto waitForData Received data goes into RSR – not visible to programmers. When RSR is full the data is put into RXREG Receive Interrupt Flag bit is set when when the RSR moves data to RXREG Can be polled or trigger an interrupt Is cleared when RXREG is read.

Pitfalls! Set TXEN before CREN Several registers in Bank 1

Extras! 9-bit transmission / reception Interrupt driven Synchronous mod