1. S4525A Peripherals & Enhanced FLASH 1 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 1 Peripherals & Enhanced FLASH New Peripherals Enhanced FLASH PIC16F87X and PIC16F62X Enhanced FLASH PIC16F87X and PIC16F62X

2. S4525A Peripherals & Enhanced FLASH 2 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 2 Peripherals & Enhanced FLASH PIC16F87X Features at a Glance l 8K x 14 FLASH Program Memory l Typ. 1000 E/W l Byte/Word Read/Write at V DD l 256 x 8 EEPROM Data Memory l Min. 100K E/W l 368 x 8 Data Memory (RAM) l 33 I/O ports l 25mA sink/source l 3 Timers l 1 - 16-bit l 2 - 8-bit l 10-bit A/D l 8K x 14 FLASH Program Memory l Typ. 1000 E/W l Byte/Word Read/Write at V DD l 256 x 8 EEPROM Data Memory l Min. 100K E/W l 368 x 8 Data Memory (RAM) l 33 I/O ports l 25mA sink/source l 3 Timers l 1 - 16-bit l 2 - 8-bit l 10-bit A/D l Two Capture/Compare/PWMs l USART l 9-bit addressable l High Speed Enhanced SPI  l All 4 SPI modes supported l Microwire  Support Master I 2 C  l Hardware Write to I 2 C devices In-Circuit-Serial Programming  l In-Circuit-Debugger l Parallel Slave Port

3. S4525A Peripherals & Enhanced FLASH 3 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 3 Peripherals & Enhanced FLASH Addressable USART: Address Feature l Asynchronous mode, 9-bit reception. l When ADDEN = 1: l RX9 = 1 indicates an address byte. l RSR contents transferred to RCREG FIFO. l Receive interrupt flag set. l RX9 = 0 indicates a data byte. l Reception is ignored. l Interrupt flag not set, next reception overwrites byte. l Asynchronous mode, 9-bit reception. l When ADDEN = 1: l RX9 = 1 indicates an address byte. l RSR contents transferred to RCREG FIFO. l Receive interrupt flag set. l RX9 = 0 indicates a data byte. l Reception is ignored. l Interrupt flag not set, next reception overwrites byte.

4. S4525A Peripherals & Enhanced FLASH 4 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 4 Peripherals & Enhanced FLASH Addressable USART: Multi-Drop Serial Interface SLAVE 1 PIC16F87X or PIC16F62X SLAVE 2 PIC16F87X or PIC16F62X SLAVE N-1 PIC16F87X or PIC16F62X SLAVE N PIC16F87X or PIC16F62X MASTER PIC16F87X or PIC16F62X 2 Wire RS-485

5. S4525A Peripherals & Enhanced FLASH 5 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 5 Peripherals & Enhanced FLASH Addressable USART: Multi-Drop Serial Interface l Addressable USART is useful for serial multi-processor communication. l Example: One master, multi-slave, 2-wire RS485 network. l Master transmits packet of data to slaves. l All slave USARTs are in 9-bit mode with the Address Enable Bit (ADDEN) set. l 1st byte has 9th bit set to indicate slave’s address. l Only addressed slave responds by setting its USART to 8 bit mode and ADDEN = 0. l Remaining data bytes in packet have 9th bit clear. l Only addressed slave gets interrupted by the data bytes. l Addressable USART is useful for serial multi-processor communication. l Example: One master, multi-slave, 2-wire RS485 network. l Master transmits packet of data to slaves. l All slave USARTs are in 9-bit mode with the Address Enable Bit (ADDEN) set. l 1st byte has 9th bit set to indicate slave’s address. l Only addressed slave responds by setting its USART to 8 bit mode and ADDEN = 0. l Remaining data bytes in packet have 9th bit clear. l Only addressed slave gets interrupted by the data bytes.

6. S4525A Peripherals & Enhanced FLASH 6 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 6 Peripherals & Enhanced FLASH Addressable USART: Receive Example b0 b1 b2 b3 b4 b5 b6 b7 b8 RC7/RX Load RSR RCIF ADDEN = 1 RX9 = 0 RSR not loaded RX9 = 1 RSR loaded Data ByteAddress Byte Slave Ignoring Data Packet

7. S4525A Peripherals & Enhanced FLASH 7 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 7 Peripherals & Enhanced FLASH Addressable USART: Receive Example RX9 = 1 RSR loaded RX9 = 0 RSR loaded Address ByteData Byte b0 b1 b2 b3 b4 b5 b6 b7 b8 RC7/RX Load RSR RCIF ADDEN Slave Accepting Data Packet

8. S4525A Peripherals & Enhanced FLASH 8 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 8 Peripherals & Enhanced FLASH Addressable USART: Other Features l Dedicated Baud Rate Generator. l Does not utilize timer resources. l Full duplex receive and transmit supported. l Two deep receive buffer. l Transmit is double buffer. l High speed mode allows operation up to 1.25 Mbaud. l Dedicated Baud Rate Generator. l Does not utilize timer resources. l Full duplex receive and transmit supported. l Two deep receive buffer. l Transmit is double buffer. l High speed mode allows operation up to 1.25 Mbaud.

9. S4525A Peripherals & Enhanced FLASH 9 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 9 Peripherals & Enhanced FLASH TXIF TXIE Interrupt TXEN Baud Rate CLK SPBRG Baud Rate Generator TX9D MSbLSb Data Bus TXREG register TSR register (8) 0 TX9 TRMTSPEN RC6/TX/CK pin Pin Buffer and Control 8  USART Transmit Block Diagram

10. S4525A Peripherals & Enhanced FLASH 10 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 10 Peripherals & Enhanced FLASH USART Receive Block Diagram x64 Baud Rate CLK SPBRG Baud Rate Generator RC7/RX/DT Pin Buffer and Control SPEN Data Recovery CREN OERR FERR RSR register MSbLSb RX9D RCREG register FIFO Interrupt RCIF RCIE Data Bus 8  64  16 or Stop Start (8) 7 10 RX9 ADDEN RX9 ADDEN RSR Enable Load of Receive Buffer 8 8 

11. S4525A Peripherals & Enhanced FLASH 11 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 11 Peripherals & Enhanced FLASH Bank0 Bank1 Bank2 Bank3 Special Function Registers PIC16C77 PIC16F877 00h 180h 1Fh 19Fh 00h 1Fh 180h 19Fh