1. INT. TO EMBEDDED SYSTEMS DEVELOPMENT
CENG 336
INT. TO EMBEDDED SYSTEMS DEVELOPMENT
Spring 2013
Recitation 07
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2. OUTLINE
LCD Driving Specs
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3. LCD
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4. LCD Pinouts Pin Level Description Connection 1 0 V Ground GND 2 +5 V
Vcc
+5V 3
Variable
Contrast Voltage
Pot. 4
H/L
"R/S“, H:DATA, L:Instruction
RC0 5
"R/W“, H:Read (Lcd →Pic), L:Write(Pic → Lcd) 6
H, H→L
"E" Clock input
RC1
7-14
I/O Pins
PORTD 15 -
Backlight anode 16
Backlight cathode
RA5(INVERTED)
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5. R/S, R/W and E
The "R/S" bit is used to select whether data or an instruction is being transferred between the microcontroller and the LCD. H:DATA, L:Instruction
H:Read (Lcd →Pic), L:Write(Pic → Lcd)
On the demo board you can make only write operations since the "R/W" pin is connected to GND.
After an instruction code or a data presented to the I/O pins a clock pulse should be sent to the "E" pin.
PORTD
On the demo board you can make only write operations since the "R/W" pin is connected to GND.
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6. Addressing and Memories Inside LCD
DDRAM : Data Display RAM is the working data buffer of the display. Each character on the display has a corresponding DDRAM location and the byte loaded in DDRAM controls which character is displayed.
Relationship between DDRAM addresses (7-bit) and positions on the liquid crystal display.
CGROM : Character Graphics ROM that holds the fixed character set, namely all the standard patterns of dots for dot matrix characters
CGRAM : Character Graphics RAM that allows the user to define special supplementary non-standard character types that are not in the CGROM. You can load your own dot pattern shapes and display them.
CGROM - stands for "Character Graphics Read only Memory". This ROM is part of the display microcontroller on the LCD and holds all the standard patterns for the 5 x 7 dot matrix characters. For instance, if you want to display character "A", you would send ASCII code 65 (decimal) to the DDRAM. The display controller looks up the pattern of dots to display for this code in the CGROM and lights up the ones appropriate for "A". The CGROM contents depend on the particular character set and model of display, US, Chinese etc. and cannot be changed. CGRAM - stands for "Character Graphics Random Access Memory" allows the user to define special supplementary non-standard character types that are not in the CGROM. You can load your own dot pattern shapes e.g. a rectangle into CGRAM and using certain reserved codes in DDRAM, call these up for display. DDRAM - stands for "Data Display Random Access Memory" and is the working data buffer of the display. Each character on the display has a corresponding DDRAM location and the byte loaded in DDRAM controls which character is displayed.
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7. The value of R/S bit: Low
LCD Instruction Codes
The value of R/S bit: Low
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8. Clear Display
Clears all display memory and returns the cursor to the home position. RS
R/W D7 D6 D5 D4 D3 D2 D1 D0 1
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9. Return Home Returns the cursor to the home position
DDRAM contents remain unchanged RS
R/W D7 D6 D5 D4 D3 D2 D1 D0 1 X
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10. Entry Mode Set
Sets the cursor move direction and specifies or not to shift the display. These operations are performed during data write and read. RS
R/W D7 D6 D5 D4 D3 D2 D1 D0 1
I/D S
I/D = 1 : Increment DDRAM address
I/D = 0 : Decrement DDRAM address
S = 1 : Display shift [I/D = 1 : Left, I/D = 0 : Right]
S = 0 : No display shift
I/D: Increments (I/D = 1) or Decrements (I/D = 0) the DD RAM address by 1 when a character code is written into or read from the DD RAM. The cursor or blink moves to the right when incremented by 1 and to the left when decremented by 1. The same applies to writing to and reading from the CG RAM.
S: Shifts the entire display either to the right or to the left when S is 1; to the left when I/D = 1 and to the right when I/D = 0. Thus it looks as if the cursor stands still and the display moves.
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11. Example entry mode settings*
Command:
Increment Address Counter
Display Shift :OFF
Command:
Decrement Address Counter
Display Shift :OFF
Command:
Display Shift :ON
Shift LEFT
Command:
Display Shift :ON
Shift RIGHT
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* images taken from:

12. Display & Cursor Control
Sets display (D), cursor (C), and blinking of cursor (B) on/off control bit. RS
R/W D7 D6 D5 D4 D3 D2 D1 D0 1 D C B
D = 1 : Display is ON
D = 0 : Display is OFF
D: The display is ON when D = 1 and OFF when D = 0. When off due to D = 0, display data remains in the DD RAM. It can be displayed immediately by setting D = 1.
C: The cursor displays when C = 1 and does not display when C = 0. Even if the cursor disappears, the function of I/D, etc. does not change during display data write. The cursor is displayed using 5 dots in the 8th line when the 5 x 7 dot character font is selected and 5 dots in the 11th line when the 5 x 10 dot character font is selected.
B: The character indicated by the cursor blinks when B = 1. The blink is displayed by switching between all blank dots and display characters at ms interval.
C = 1 : Cursor ON
C = 0 : Cursor OFF
B = 1 : Blink ON
B = 0 : Blink OFF
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13. Cursor or Display Shift
Moves the cursor or shifts the display without changing DD RAM contents. RS
R/W D7 D6 D5 D4 D3 D2 D1 D0 1
S/C
R/L X
S/C
R/L
Operation
The cursor position is shifted to the left 1
The cursor position is shifted to the right
The entire display is shifted to the left with the cursor
The entire display is shifted to the right with the cursor
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14. Function Set
Sets interface data length (DL), number of display lines (N), and character font (F). RS
R/W D7 D6 D5 D4 D3 D2 D1 D0 1 DL N F X
F = 1 : 5x11 dots
F = 0 : 5x8 dots
N = 1 : 2 lines
N = 0 : 1 line
DL = 1 : 8-bit
DL = 0 : 4-bit
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15. Set DDRAM Address Sets the DDRAM addressRS
R/W D7 D6 D5 D4 D3 D2 D1 D0 1 A6 A5 A4 A3 A2 A1 A0
Relationship between I/O port (PORTD in our case) values and positions on the liquid crystal display.
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16. Set CGRAM Address Sets the CGRAM address RS R/W D7 D6 D5 D4 D3 D2 D11 A5 A4 A3 A2 A1 A0
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17. Write Data to RAM Writes data into the RAM RS R/W D7 D6 D5 D4 D3 D2 D1
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18. Serial Communication -Introduction
PIC16F877 has two serial I/O modules:
The Universal Synchronous Asynchronous Receiver Transmitter (USART) module
Asynchronous (full duplex)
Synchronous - Master (half duplex)
Synchronous - Slave (half duplex)
Master Synchronous Serial Port (MSSP)
SPI mode
I2C mode
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19. USART
Universal Synchronous and Asynchronous serial Receiver and Transmitter
A standard I/O device that provides conversions between serial and parallel data
RS232
This is a standard specification for the physical layer of a serial data interchange
Specifies physical connections and voltage levels
Data is transferred as a series of bits represented by voltage levels varying over time
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20. Asynchronous Serial Communication – Cont.
The transmit line idle signal is 1 (mark)
The transmitter signals the start of a frame by asserting a 0 (space) on TX
At regular intervals (the baud rate), the transmitter asserts the bits of data, least significant first
One or two stop bits (1) terminate the frame
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21. Synchronous Serial Communication
For synchronous communication, only three lines are needed
Common ground
Data (DT)
Clock(CK)
Half-duplex
Transmission and reception do not occur at the same time.
Gnd
Gnd DT DT CK CK
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22. USART Asynchronous Mode
In this mode, the USART uses standard non-return-to-zero (NRZ) format (one start bit, eight or nine data bits and one stop bit).
The USART transmits and receives the LSb first.
Parity is not supported by the hardware, but can be implemented in software (stored as the ninth
data bit).
Asynchronous mode is stopped during SLEEP.
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23. Transmitter Block Diagram
The USART transmitter block diagram is shown in Figure The heart of the transmitter is the
transmit (serial) shift register (TSR). The shift register obtains its data from the read/write transmit
buffer, TXREG. The TXREG register is loaded with data in software. The TSR register is not
loaded until the STOP bit has been transmitted from the previous load. As soon as the STOP bit
is transmitted, the TSR is loaded with new data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register
is empty and the TXIF flag bit is set. This interrupt can be enabled/disabled by setting/clearing
the TXIE enable bit. The TXIF flag bit will be set regardless of the state of the TXIE enable bit and
cannot be cleared in software. It will reset only when new data is loaded into the TXREG register.
While the TXIF flag bit indicated the status of the TXREG register, the TRMT bit (TXSTA<1>)
shows the status of the TSR register. The TRMT status bit is a read only bit which is set when
the TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in
order to determine if the TSR register is empty.
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24. Receiver Block Diagram
The receiver block diagram is shown in Figure The data is received on the RX/DT pin and
drives the data recovery block. The data recovery block is actually a high speed shifter operating
at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at
FOSC.
Once Asynchronous mode is selected, reception is enabled by setting the CREN bit
(RCSTA<4>).
The heart of the receiver is the receive (serial) shift register (RSR). After sampling the RX/TX pin
for the STOP bit, the received data in the RSR is transferred to the RCREG register (if it is empty).
If the transfer is complete, the RCIF flag bit is set. The actual interrupt can be enabled/disabled
by setting/clearing the RCIE enable bit. The RCIF flag bit is a read only bit which is cleared by
the hardware. It is cleared when the RCREG register has been read and is empty. The RCREG
is a double buffered register, i.e. it is a two deep FIFO. It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a third byte begin shifting to the RSR register.
On the detection of the STOP bit of the third byte, if the RCREG register is still full then overrun
error bit, OERR (RCSTA<1>), will be set. The word in the RSR will be lost. The RCREG register
can be read twice to retrieve the two bytes in the FIFO. The OERR bit has to be cleared in software.
This is done by resetting the receive logic (the CREN bit is cleared and then set). If the
OERR bit is set, transfers from the RSR register to the RCREG register are inhibited, so it is
essential to clear the OERR bit if it is set. Framing error bit, FERR (RCSTA<2>), is set if a stop
bit is detected as a low level. The FERR bit and the 9th receive bit are buffered the same way as
the receive data. Reading the RCREG will load the RX9D and FERR bits with new values, therefore
it is essential for the user to read the RCSTA register before reading the next RCREG register
in order not to lose the old (previous) information in the FERR and RX9D bits.
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25. TXSTA Register
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26. RCSTA Register
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27. USART Baud Rate Generator
SPBRG register controls the period
In asynchronous mode BRGH (TXSTA<2>) also controls the baud rate. In synchronous mode bit BRGH is ignored.
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28. RC7/RX/DT pins for the USART.
The SPEN bit (RCSTA<7>), and the TRIS bits, have to be set in order to configure the RC6/TX/CK and
RC7/RX/DT pins for the USART.
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29. USART Asynchronous Transmission
Steps to follow when setting up a Asynchronous Transmission:
1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set the BRGH bit.
2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit.
3. If interrupts are desired, then set the TXIE, GIE and PEIE bits.
4. If 9-bit transmission is desired, then set the TX9 bit.
5. Enable the transmission by setting the TXEN bit, which will also set the TXIF bit.
6. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit.
7. Load data to the TXREG register (starts transmission).
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30. USART Asynchronous Reception
Steps to follow when setting up an Asynchronous Reception:
1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH.
2. Enable the asynchronous serial port by clearing the SYNC bit, and setting the SPEN bit.
3. If interrupts are desired, then set the RCIE, GIE and PEIE bits.
4. If 9-bit reception is desired, then set the RX9 bit.
5. Enable the reception by setting the CREN bit.
6. The RCIF flag bit will be set when reception is complete and an interrupt will be generated if the RCIE bit was set.
7. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception.
8. Read the 8-bit received data by reading the RCREG register.
9. If any error occurred, clear the error by clearing the CREN bit.
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31. Timing Diagrams [1/3]
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32. Timing Diagrams [2/3] A third write to TXREG overwrites Word2 3.5.2013
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33. Timing Diagrams [3/3]
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