Topics Modeling with hardware description languages (HDLs).

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Presentation transcript:

Topics Modeling with hardware description languages (HDLs).

Hardware description languages Textual languages for describing hardware: structure; function. Most people today use textual languages rather than schematics for most digital design. Schematics make poor use of screen space.

Major HDLs Two major HDLs designed for simulation: VHDL; Verilog. Similar capabilities but somewhat different language philosophies. EDIF is a standard netlist format.

Simulation vs. programming Simulation tags computations with times. Must know when signals change to properly simulate hardware. Simulation is parallel. Many statements can execute at the same (simulation) time. Just like hardware.

Types of simulation Compiled code simulation. Event-driven simulation. Generate program that evaluates a hardware block. Operational details within the hardware block are lost. Event-driven simulation. Propagate events through simulation. Don’t simulate a block until its inputs change.

Event-driven simulation An event is a change in a net’s value. An event has two components: value; time. net1 t=35 ns time net net1=0 @ 35 ns event

Events on a gate Propagate events only when nets change value. If an input change doesn’t cause an output change, no event is propagated. 1 no event 1 1

Timewheel The timewheel is a data structure in the simulator that efficiently determines the order of events processed. Events are placed on the timewheel in time order. Events are taken out of the head of the timewheel to process them in order.

Timewheel operation c=0 @ 2 ns a c 1 b=1 @ 1 ns 1 1 time b a=1 @ 0 ns a c 1 b=1 @ 1 ns 1 1 time b a=1 @ 0 ns netlist timewheel

Order of evaluation Order of evaluation is important. Causality must be obeyed. Evaluating events in the wrong order can cause inaccurate results.

Order of evaluation example e=0 @ 4 ns a c 1 1 d=1 @ 2 ns 1 b=1 @ 1 ns 1 e time b d netlist timewheel

Compiled simulation A block of code is generated to simulate a block of hardware. Can use compiler to optimize the code. Code ignores much temporal behavior within the block. Must still evaluate events in the right order. Must generate times at interface to event-driven model.

Modeling Structural modeling describes the connections between components. Netlists are structural models. Behavioral models describes the functional relationship between inputs and outputs. Similar to programming but values are events.

HDLs language constructs Must be able to define component types. A model may be behavioral or structural. May be able to define abstract data types. A wire may carry an enumerated value. Multi-valued simulation may be defined using abstract data types. May be able to define modules to control the scope of names.

Testbenches A testbench is a model used to exercise a simulation. Provides stimulus. Checks outputs. Testbenches help automate design verification. Rerun edited module against testbench. Run models at behavioral, RTL levels against the same testbench.

Synthesis subsets VHDL and Verilog were designed for simulation. A synthesis subset is: synthesizable; produces consistent simulation results. Different tools may use different synthesis subsets.

Register-transfer synthesis Most common type of synthesis. Synthesizes gates from abstract RT model. Registers are explicit. Some tools will infer storage elements---be careful. Optimized for performance, area, power.