Memory Address Space and Data Organization The 8088 microcomputer supports 1 Mbytes of external memory. The memory of an 8088-based microcomputer is organized as 8-bit bytes, not as 16-bit words. Memory address space of the 8088/8086 microcomputer

Memory Address Space and Data Organization The 8088 can access two consecutive bytes as word of data. Lower address byte and higher address byte The two bytes represent the word 01010101000000102 = 550216

Memory Address Space and Data Organization EXAMPLE What is the data word shown in the previous figure? Express the result in hexadecimal form. Is it stored at an even- or odd addressed word boundary? Is it an aligned or misaligned word of data? Solution: 111111012 = FD16 = FDH 101010102 = AA16 = AAH Together the two bytes give the word 11111101101010102 = FDAA16 = FDAAH Expressing the address of the least significant byte in binary form gives 0072BH = 0072B16 = 000000000111001010112, Therefore, it is misaligned word of data.

Memory Address Space and Data Organization Even- or odd-addressed word If the least significant bit of the address is 0, the word is said to be held at an even addressed boundary. Aligned word or misaligned word

Memory Address Space and Data Organization A double word corresponds to four consecutive bytes of data stored in memory. Example of double word data is pointer. A pointer is a two-word address element that is used to access data or code in memory

Memory Address Space and Data Organization A pointer is a double word. The higher address word represents the segment base address while the lower address word represents the offset . Example: Segment base address = 3B4C16 = 00111011010011002 Offset value = 006516 = 00000000011001012

Memory Address Space and Data Organization EXAMPLE How should the pointer with segment base address equal to A00016 and offset address 55FF16 be stored at an even-address boundary starting at 0000816? Is the double word aligned or misaligned? Solution: Storage of the two-word pointer requires four consecutive byte locations in memory, starting at address 0000816. The least significant byte of the offset is stored at address 0000816 and is shown as FF16 in the previous figure. The most significant byte of the offset, 5516, is stored at address 0000916. These two bytes are followed by the least significant byte of the segment base address, 0016, at address 0000A16, and its most significant byte, A016, at address 0000B16. Since the double word is stored in memory starting at address 0000816, it is aligned.

Generating a Memory Address A logical address in the 8088 microcomputer system is described by a segment base and an offset. The physical addresses that are used to access memory are 20 bits in length. The generation of the physical address involves combining a 16-bit offset value that is located in the instruction pointer, a base pointer, an index register, or a pointer register and a 16-bit segment base value that is located in one of the segment register.

Generating a Memory Address

Generating a Memory Address

Generating a Memory Address

Generating a Memory Address EXAMPLE What would be the offset required to map to physical address location 002C316 if the contents of the corresponding segment register are 002A16? Solution: The offset value can be obtained by shifting the contents of the segment of the segment register left by four bit positions and then subtracting from the physical address. Shifting left give 002A016 Now subtracting, we get the value of the offset: 002C316 – 002A016 = 002316

Generating a Memory Address Different logical addresses can be mapped to the same physical address location in memory.

Hardware Organization of the Memory Address Space– 8088 Microprocessor 8088 memory hardware is organized as a single byte- wide memory bank Size—1M X 8 bits Physical address range— 0H–FFFFFH Address/data bus demultiplexed in external hardware Input: 20-bit address bus— A19 through A0 Input/Output: 8-bit data bus—D7 Through D0

Hardware Organization of the Memory Address Space– 8088 Microprocessor Byte access bus cycle • MPU applies address of storage location to be accessed over address lines A19-A0. A19—most significant bit A0—least significant bit Byte of data written into or read from address X transferred over data lines D0 through D7. D7—most significant bit D0—least significant bit Byte access takes a minimum of one bus cycle of duration @5MHz—800ns @8MHz—500ns Word access bus cycles MPU must access two consecutive storage locations in memory—X and X+1. Requires two bus cycles. Address X accessed during cycle 1. Address X+1 accessed during cycle 2 Word access duration is a minimum of two bus cycle @5MHz—2 X 800ns = 1600ns @8MHz—2 X 500ns = 1000ns

Hardware Organization of the Memory Address Space– 8088 Microprocessor 8086 memory hardware is organized as a two byt ewide memory bank. Bank size—512K X 8 bits. Low- bank holds even addressed bytes—0H through FFFFEH High-bank holds odd addressed bytes—1H through FFFFFH Address/data bus demultiplexed in external hardware Input: 20-bit+ address bus— A19 through A0, and BHE*. A1-A19 = selects storage location. A0 = 0 enables low bank. BHE* = 0 enables high bank Input/Output: 16-bit data bus—D15 Through D0. D7-D0 even addressed byte accesses D15-D8: odd addressed byte accesses D15-D0: word accesses

Hardware Organization of the Memory Address Space– 8088 Microprocessor

Hardware Organization of the Memory Address Space– 8088 Microprocessor

Address Bus Status Code During memory bus cycle an address bus status code s4,s3 is output by processor, these status code is multiplexed with address bits A17and A16. Bits S4 and S3 together forma 2bit binary code that identifies which one of the four segment registers was used to generate the physical address that output during the address period in the current bus cycle. S4 S3 Address Status ES 1 SS CS DS

Memory Control Signals– 8088 Minimum-Mode Control Signals ALE = pulse to logic 1 tells bus interface circuitry to latch address RD* = logic 0 tells memory subsystem that a code or data read is in progress WR*= logic 0 tells memory subsystem that a data write is in progress IO/M*= Logic 0 tells interface circuits that the data transfer operation is for the memory subsystem DT/R* = logic 1 & 0. sets the direction of the external data bus for read(input) or write(output) operation DEN*= logic 0, enables the interface between the memory subsystem and MPU data bus SSO* = tells memory interface whether the memory access is a code read or data access. Logic 0 for instruction code read

Memory Control Signals– 8088 Maximum-Mode Control Signals 8288 bus controller produces the control signals MRDC* replaces RD* MWTC* and AMWC* replace WR* DEN is complement of DEN* IO/M* no longer needed (bus controller creates separate memory and IO read/write controls) • SSO* no longer part of interface

Memory Control Signals– 8088 Maximum-Mode Control Signals During all memory accesses one of three bus cycle status code are output by the MPU Instruction fetch • Read memory • Write memory 8288 decodes to produce appropriate control command signals MRDC*-- instruction fetch/memory read MWTC* -- memory write AMWC* -- advanced memory write

𝑸𝑺 𝟎 , 𝑸 𝑺 𝟏 (Queue Status) The processor provides the status of queue in these lines. The queue status can be used by external device to track the internal status of the queue in 8086. The output on QS0 and QS1 can be interpreted as shown in the table.

𝐋𝐎𝐂𝐊 An output signal activated by the LOCK prefix instruction. Remains active until the completion of the instruction prefixed by LOCK. The 8086 output low on the 𝐋𝐎𝐂𝐊 pin while executing an instruction prefixed by LOCK to prevent other bus masters from gaining control of the system bus.

Read and Write Bus Cycles– 8088 Minimum Mode Read Bus Cycle T1 state—read cycle begins • Address output on A0-A19 • Pulse produced at ALE--address should be latched in external circuitry on trailing edge of ALE • IO/M* set to 0 memory bus cycle DT/R* set to 0 set external data bus control circuitry for receive mode (read)

Read and Write Bus Cycles– 8088 Minimum Mode Read Bus Cycle T2 state • Status code output on S3-S6 • AD0 through AD7 tri-stated in preparation for data bus operation • RD* set to 0 read cycle • DEN* set to 0 enable external data bus control circuitry

Read and Write Bus Cycles– 8088 Minimum Mode Read Bus Cycle T3 state • Data on D0-D7 read by the MPU

Read and Write Bus Cycles– 8088 Minimum Mode Read Bus Cycle T4 state—read cycle finishes • RD* returns to 1 inactive level • Complete address/data bus tri-stated • IO/M* returned to 1 IO bus cycle • DEN* returned to 1 inactive level • DT/R* returns to 1 transmit level

Differences of 8086 read bus cycle BHE* is output along with the address in T1 Data read by the MPU can be carried over all 16 data bus lines M/IO*—which replaces IO/M*—switches to 1 instead of 0 at the beginning of T1 SSO* signals is not produce

8088 Minimum Mode Write Bus Cycle T1 state—write cycle begins • Address output on A0-A19 • Pulse produced at ALE and address latched in external circuitry on trailing edge of ALE • IO/M* set to 0 -> memory bus cycle • DT/R* remains at 1 -> external data bus control circuitry for transmit mode (write)

8088 Minimum Mode Write Bus Cycle T2 state • Status code output on S3-S6 • AD0 through AD7 transitioned to data bus and write data placed on bus • DEN* set to 0 -> enable external data bus control circuitry • WR* set to 0 -> write cycle

8088 Minimum Mode Write Bus Cycle T3 or T4 state • Data on D0-D7 written into memory (memory decides when!) • T4 state—write cycle finishes • WR* returns to 1 inactive level • Complete address/data bus tri-stated • IO/M* returned to 1 -> IO bus cycle • DEN* returned to 1-> inactive level

8086 Maximum Mode Write Bus Cycle Address and data transfer operation identical Transfer may be a high-byte, lowbyte, word Differences is the 8288 produces the bus control signals—ALE, DEN, AMWC*, and MWTC*

8086 Maximum Mode Write Bus Cycle Bus status code S2*-S0* output prior to T1 and held through T2 AMWC* and MWTC* replace WR* (Note timing difference) DEN =1 produced instead of DEN* =0 (change in external circuitry!)

PROGRAM AND DATA STORAGE MEMORY Secondary storage memory is used for storage of data, information, and programs that are not in use. This part of the memory unit can be slow speed But require very large storage capacity. Primary storage memory is used for working information, such as the instructions of the program currently being run and data that it is processing. This section normally requires high-speed operation but does not normally require very large storage capacity.

PROGRAM AND DATA STORAGE MEMORY Primary storage memory is further partitioned into program storage memory and data storage memory. The much larger part of the program storage memory in a PC is built with dynamic random access read/write memory devices ( DRAMS). They may be either mounted on the main processor board or on an add-in memory module or board. Its purpose is to store programs that are to be executed, but in this case they are loaded into memory only when needed. Information that frequently changes is stored in the data storage part of the microcomputer‘s memory subsystem.

PROGRAM AND DATA STORAGE MEMORY

RANDOM ACCESS READ/WRITE MEMORIES RAM is similar to ROM in that its storage location can be accessed in a random order, but it is different from ROM in two important ways: First. RAM can be used to save data by writing to it, and then reading back for additional processing. Second. RAM is volatile that is, if power is removed from RAM, the stored data are lost

RANDOM ACCESS READ/WRITE MEMORIES Random Access Read/Write Memory (RAM) Used for temporary storage of data and program information Stored information can be altered by MPU—read or written Information read from RAM Modified by processing Written back to RAM for reuse at a later time Information normally more frequently randomly accessed than ROM Information is volatile— lost when power turns off

RANDOM ACCESS READ/WRITE MEMORIES Types: Static RAM (SRAM)— data once entered remains valid as long as power supply is not turned off • Lower densities • Higher cost • Higher speeds DRAM—data once entered requires both the power to be maintained and a periodic refresh • Higher densities • Lower cost • Lower speeds • Refresh requires additional circuitry

RANDOM ACCESS READ/WRITE MEMORIES Static and Dynamic RAMs For a Static RAM (SRAM) , data once entered, remain valid as long as the power supply is not turned off. To retain data in a Dynamic RAM (DRAM), we must both keep the power supply turned on and periodically restore the data in each storage location. This added requirements necessary because the storage elements in a DRAM are capacitive nodes. If the storage nodes are not recharged within a specific interval of time, data are lost. This recharging process is known as refreshing the DRAM.

Standard Dynamic RAM ICs Dynamic RAMS are available in higher densities than static RAMS Some other benefits of using DRAMS over SRAMS are that: They cost less, consume less power. Their 16-and 18-pin packages take up less space. For these reasons DRAMS are normally used in applications that require a large amount of memory. For example most systems that support at least 1Mbyte of data memory are designed using DRAMS.

DRAM BLOCK DIAGRAM DRAM signal interfaces Address multiplexed in external circuitry into a separate row and column address Row address = A7-A0 Column address = A15-A8 Special RAS* and CAS* inputs used to strobe address into DRAM Row and column addresses applied at different times to address inputs A0 through A7 Row address first Column address second Known as “RAS before CAS” Address reassembled into 16-bit address inside

DRAM BLOCK DIAGRAM DRAM signal interfaces Address multiplexed in external circuitry into a separate row and column address Row address = A7-A0 Column address = A15-A8 Special RAS* and CAS* inputs used to strobe address into DRAM Row and column addresses applied at different times to address inputs A0 through A7 Row address first Column address second Known as “RAS before CAS” Address reassembled into 16-bit address inside

DRAM BLOCK DIAGRAM DRAM Frequently data organizations are X1, X2, and X4 Separate data inputs and outputs Data input labeled D Data output labeled Q Read/write (W) input signals read or write operation

Block diagram of 2164 DRAM

DRAM BLOCK DIAGRAM The 21648 is one of the older NMOS DRAM devices. Looking at the block diagram, we find that it has eight address inputs, A0 through A 7, a data input and data output marked D and Q, respectivly and three control inputs, rowaddress stmbe (RAS), column addrcss stnbe (CAS), and

Types of I/O for 8088/8086 Input/output system allows peripherals to: Provide data or Receive results after processing the data Implemented using I/O ports Employs two different types of I/O: Isolated I/O. Memory mapped I/O. Method differs in how I/O ports are mapped into MPU’s address spaces. Some microcomputer employs both method.

Isolated I/O I/O devices treated separately from memory. Hardware and software architecture of 8088/8086 support separate memory I/O address space. Can be accessed as either byte-wide or word-wide. Can be treated as either independent byte-wide I/O ports or word-wide I/O ports. Page 0: Certain I/O instructions can only perform operations to ports in this part of the address range. Other I/O instructions can input/output data for ports anywhere in the address space. Separate memory I/O address space (64 Kbytes)  0000H – FFFFH.

Isolated I/O FFFF Port 65 535 I/O address space 00FF Port 255 00FE . 0004 Port 4 0003 Port 3 0002 Port 2 0001 Port 1 0000 Port 0 Page 0 Port 1 (16 bit port) Port 0 (16 bit port)

Isolated I/O Advantages: 1 MByte memory address space is available for use with memory. Special instructions have been provided in the instruction set of 8088/8086 to perform isolated I/O input and output operations. These instructions have been tailored to maximize I/O performance. Disadvantages: All input and output data transfers must take place between AL or AX register and the I/O port.

Memory-mapped I/O I/O devices is placed in memory address space of the microcomputer. The memory address space is assigned to I/O devices. MPU looks at the I/O port as though it is a storage location in memory. Make use of instructions that affect data in memory rather than special input/output instructions. i.e. AND content port 0 with (internal register) rather than AL, or AX.

Memory-mapped I/O FFFFF : Port 4095 Memory address space : I/O ports E0FFF I/O ports E0003 E0002 E0001 E0000 00001 00000 Port 4095 : I/O ports Port 3 Port 2 Port 1 Port 0 I/O addresses Port 1 (16 bit port) Port 0 (16 bit port)

Memory-mapped I/O Advantages: Many more instructions and addressing modes are available to perform I/O operations. I/O transfers can now take place between I/O port and internal registers other than just AL/AX. Disadvantages: Memory instructions tend to execute slower than those specifically designed for isolated I/O. Part of the memory address space is lost. i.e. AND content port 0 with (internal register) rather than AL, or AX.

Isolated Input/Output Interface The interface permits 8088/8086 microcomputers to communicate with the outside world The interface between MPU and I/O is similar to MPU and memory Input output data transfers also take place over the multiplexed address/data bus Through this I/O interface, the MPU can input or output data in bit, byte or word (8086) formats

Isolated Input Output Interface :: Minimum-mode Interface Minimum-mode 8088 system I/O interface

Isolated Input Output Interface :: Minimum-mode Interface Minimum-mode 8086 system I/O interface

Isolated Input Output Interface :: Minimum-mode Interface Example of I/O device: Keyboard (input). Printer (output). Asynchronous serial communications port (input/output) Circuits in the interface section must perform functions such as: Select I/O port. Latch output data. Sample input data. Synchronize data transfers. I/O ports for devices 0 through N. can be represented as keyboard, etc. 3. Translate between TTL voltage levels and those required to operate I/O devices.

Isolated Input Output Interface :: Minimum-mode Interface (8088) Data/Address Lines: Multiplexed address/data bus. Only 16 least significant lines used. AD0-AD7 and A8-A15 Control Signals: Similar to memory interface. Difference between 8088 and 8086. Complete data bus used for data transfer. AD0-AD15. M/IO complement of IO/M. SSO replaced with BHE.

Isolated Input Output Interface :: Maximum-mode Interface Maximum-mode 8088 system I/O interface Maximum-mode 8086 system I/O interface

Isolated Input Output Interface :: Maximum-mode Interface (8088/86) 8288 bus controller produces control signals for the I/O subsystems. Decoded S2S1S0 will determine which type of bus cycle is in progress. If code corresponds to: I/O read bus cycle , 8288 generates IORC. I/O write bus cycle, then IOWC and AIOWC generated. 8288 also produces ALE, DT/R and DEN control signals. Data and addresses are transferred over AD0-AD7 and A8-A15. 8086 differs from 8088 as follows: 16 bit data bus is the path for data transfers. Signal BHE is included.

Input Output Data Transfers Byte-wide or word-wide. I/O address used to select the input/output port to be accessed. I/O address specified as part of the instruction that performs the I/O operation. The addresses: 16 bits in length. Output over AD0 (LSb) – AD7 and A8-A15 (MSb). The most significant address lines A16-A19 = 0 during address period (T1) of all bus cycles. IO/M determines I/O operations. Held at 1 during the complete input/output bus cycles. I/O address space = 64 K byte-wide (16 bits address). Can be used to enable the address latch or address decoder in external I/O circuitry.

Input Output Data Transfers Performed over data bus. Byte-wide transfers = 1 cycle (D0-D7). Word-wide transfers require two bus cycles. Two consecutive byte-wide data transfers. Data transfer (8086): The addresses are output on address/data bus lines AD0-AD15. A0 and BHE determine whether access at odd-addressed byte-wide port, even- addressed byte-wide port or word-wide port. i.e. A0BHE = 10  odd-addressed byte wide I/O port is accessed.

Input Output Data Transfers Even and odd addressed byte transfer require 1 bus cycle. Even-addressed byte transfer  D0-D7. Odd-addressed byte transfer  D8-D15. Word data transfer can either require one or two bus cycles . Word data transfer performed over D0-D15. One cycle word transfer  I/O port is aligned at even address boundaries. Two cycles word transfer  Misaligned word.

Input Output Instructions Isolated I/O mode uses special input and output instructions together with I/O port addressing modes. Can either be direct or variable I/O instructions. Can be used to transfer byte/word. All data transfer take place over I/O device and accumulator register (AL/AX). Known as accumulator I/O. Byte/word wide transfer determined by AL/AX.

Input Output Instructions Mnemonic Meaning Format Operation IN Input direct IN Acc, Prt (Acc)  (Port) Acc = AL or AX Input indirect (variable) IN Acc, DX (Acc)  ((DX)) OUT Output direct OUT Prt, Acc (Port)  (Acc) Output indirect (variable) OUT DX, Acc ((DX))  (Acc) Input/output instructions

Input Output Instructions :: Direct I/O Instructions Address of the I/O port: Specified as part of the instruction. 8 bits provided for direct address, thus: Address range is limited to 0016-FF16. This range is referred as page 0 in I/O address space. i.e. IN AL, 0FEH (AL)  (FE16) Content of address FE to be input to the AL register. Only one bus cycle.

Input Output Instructions :: Direct I/O Instructions Example 2: Write a sequence of instructions that will output the data 3416 to a byte-wide output port at address 8916 of the I/O address space. MOV AL, 0FFH OUT 0ABH, AL

Input Output Instructions Difference between direct and variable: The way in which the address of the I/O port is specified. Direct  8 bit address is specified as part of the instruction. Variable  use 16 bit address in DX register. (DX) is not an offset but actual address. Variable I/O instructions can access ports located anywhere in the 64 K byte I/O address space. Data/address must be loaded into or removed from AL/AX/DX before another input or output operation can be performed. (DX) is not an offset but actual address that is to be output on AD0 (LSB) – AD7 and A8-A15 during I/O bus cycles. MOV DX 0A000H IN AL, DX MOV BL, AL Inputs the contents of byte-wide input port at A000 of the I/O address space into AL and then saves in BL.

Input Output Instructions Example 2: Write a program that will output DA16 to an output port located at address EA2016 of the I/O address space. Data are to be read in from two byte-wide input ports at address AA16 and BA16 and then output as a word-wide output port at address B00016. Write a program to perform this input/output operation.

Input Output Bus Cycles Signals (minimum-mode) similar to those involved in memory interface. Function, logic levels and timing of all signals other than IO/M are identical to section 8.11. IO/M changes at logic level, not the timing.

Input Bus Cycles :: 8088 T1: IO/M =1 and maintained throughout the cycle. Indicate IO operation. ALE output together with address. DEN =0. Signals interface circuitry when to put data onto the bus. 8088 reads data off the bus during period T3. Input bus cycle of the 8088

Output Bus Cycles :: 8088 8088 puts data on the bus late in T2 and maintains it during the rest of the bus cycle. This time WR = 0. Signals I/O system that valid data are on the bus. Output bus cycle of the 8088

Input Bus Cycles :: 8086 Differences: BHE output along with address in state T1. Used with A0 to select even/odd address byte/word wide port. Data transfer over 16 bit address/data bus at T3. M/IO replaces IO/M. SSO = none.