Digital Electronics Flip-Flops

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Presentation transcript:

Digital Electronics Flip-Flops by Norazian Subari Fakulti Kejuruteraan Elektrik & Elektronik aziansubari@ump.edu.my

Chapter Description Expected Outcomes At the end of this topic, students should be able to: Understand the operation of a latch flip-flops. Understand the operation of a edge-triggered flip-flops. Draw the output timing waveforms of several types of flip-flops in response to a set of input signals.

Topics NAND Gate Latch NOR Gate Latch Clock Signals and Clocked Flip-Flops Clocked S-R, J-K and D Flip-Flop D Latch

Sequential logic circuits Flip=Flop Latch

Latch Set Reset (SR) Two Type NAND Gate Latch NOR Gate Latch Set (S) input : HIGH or 1 state Reset (R) input : LOW or 0 state Two Type NAND Gate Latch NOR Gate Latch

NAND GATE Latch

NAND GATE Latch

NOR GATE Latch

Clocked signal and clocked flip-flop

Clocked S-R flip-flop

Clocked J-K flip-flop

Clocked D flip-flop

D latch (transparent latch)

References T. Floyd, “Digital Fundamental”, 10th Ed., USA : Prentice-Hall, 2008. R.J. Tocci, “Digital Systems: Principles and Applications”, 10th Ed., USA : Prentice-Hall, 2006.

Norazian Subari Fakulti Kejuruteraan Elektrik & Elektronik Universiti Malaysia Pahang 26600 Pekan, Pahang, Malaysia http://fkee.ump.edu.my/index.php/en/staff-menu/articles-staff/1622-norazian-subari-main-profile