Atomistic Modeling of Electronic Structure and Transport in Disordered Nanostructures Neerav Kharche Advisors: Prof. Gerhard Klimeck Prof. Timothy Boykin PhD Final Examination January 15, 2010

Moore’s Law From http://www.intel.com/technology/mooreslaw/index.htm Historical Development: 1) Four decades of steady scaling 2) Present day MOSFETs are nanoscale (LG~30nm) 3) Scaling is motivated by performance and integration density issues 4) Moore’s Law describes this steady growth 4) ITRS guides the future scaling trends Scaling Issues and Challenges: 1) Implementation of Moore’s law becoming challenging 2) Off-state leakage limits scaling of planar CMOS 3) Additional gates needed to curb SCE (dual/tri-gate) 4) Gate oxide scaling reached the limit (direct tunneling) 5) High-κ dielectric + metal gate in near future From http://www.intel.com/technology/mooreslaw/index.htm

Nanoelectronic Device Scaling Channel doping S/D doping Strained channel New gate dielectrics Device geometries Channel materials High-k dielectrics 2015-2019 Research Acknowledgement: Robert Chau, Intel III-V channel devices Emerging QC devices Low-power & powerful QC algorithms Low-power & high-speed 3

Atomic Scale Disorders in Nanoscale Devices Novel channel materials InAs InGaAs ~ 4 nm In Ga As D.H. Kim et. al., EDL 2008 Alloy disorder Quantum Computing devices Si SiGe Interface roughness Friesen et al., PRB, 2003 Goswami et al., Nature Physics, 2007 4

Tight-Binding Approach (1) Bandstructure and effective mass Carrier confinement Atomic scale material variations Local strain variations Atomistic treatment of electric and magnetic fields InGaAs InAs InGaAs

Tight-Binding Approach (2) Valley-splitting Highly dependent on atomic scale thickness variations Need atomistic modeling technique such as tight-binding SiGe/SiO2 Si (001) 2nd Single valley L Two valleys Si Boykin et al., APL. 2004

Outline Motivation Tight-Binding Approach to Model Atomic Scale Variations Summary of Results Valley Degeneracies in (111) Si Quantum Wells Valley-Splitting in (100) SiGe/Si/SiGe Quantum Wells Transport Characteristics of AlGaAs Nanowires Ultra-Scaled InAs HEMTs Performance Analysis of Ultra-Scaled InAs HEMTs Modeling Approach Comparison to Experiments Scaling Considerations Summary of Contributions Outlook

Outline Motivation Tight-Binding Approach to Model Atomic Scale Variations Summary of Results Valley Degeneracies in (111) Si Quantum Wells Valley-Splitting in (100) SiGe/Si/SiGe Quantum Wells Transport Characteristics of AlGaAs Nanowires Ultra-Scaled InAs HEMTs Performance Analysis of Ultra-Scaled InAs HEMTs Modeling Approach Comparison to Experiments Scaling Considerations Summary of Contributions Outlook

Valley Degeneracies in (111) Si Quantum Wells Theory: 6 fold Expt: 2 & 4 fold Objective Resolve discrepancies in experimentally observed and theoretically predicted valley degeneracies Effect of surface miscut on the electronic structure Approach Supercell tight-binding approach to model surface miscuts Effective mass based valley-projection model to determine the directions of valley-minima of large supercells Insight Atomistic basis representation is essential to capture the effect of mono-atomic steps resulting from miscut Results Flat (111) Si QW shows 6 fold valley degeneracy Miscut causes 2-4 splitting due to different effective masses in confinement direction Expt: Eng et al., PRL., 2007 Theory: Kharche et al., APL. 2009

Outline Motivation Tight-Binding Approach to Model Atomic Scale Variations Summary of Results Valley Degeneracies in (111) Si Quantum Wells Valley-Splitting in (100) SiGe/Si/SiGe Quantum Wells Transport Characteristics of AlGaAs Nanowires Ultra-Scaled InAs HEMTs Performance Analysis of Ultra-Scaled InAs HEMTs Modeling Approach Comparison to Experiments Scaling Considerations Summary of Contributions Outlook

Valley-Splitting in (100) SiGe/Si/SiGe Quantum Wells Objective: Model experimentally observed valley splitting in strained (100) SiGe/Si/SiGe quantum wells Resolve discrepancies in experiment and theory Approach: Model large structure 150nm x 16nm x 15nm 10 million atoms No changes to the published tight binding parameters Result: Match experiment well Atomic disorder critical in the device understanding Quantitative model of complex system Δs Δv Valley + spin splitting Valley QC states Strain – 10 million atoms Elect. – 2 million 150 nm 16 nm 10 nm 15 nm Si SiGe Valley + spin splitting Δs Δv Valley QC states E0 E1 E2 E3 Si SiGe Alloy disorder SiGe Si (001) Rough steps Expt: Goswami, Nature Physics, 2007 Theory: Kharche et al., APL., 2007 11

Outline Motivation Tight-Binding Approach to Model Atomic Scale Variations Summary of Results Valley Degeneracies in (111) Si Quantum Wells Valley-Splitting in (100) SiGe/Si/SiGe Quantum Wells Transport Characteristics of InAlAs Nanowires Ultra-Scaled InAs HEMTs Performance Analysis of Ultra-Scaled InAs HEMTs Modeling Approach Comparison to Experiments Scaling Considerations Summary of Contributions Outlook

Electronic Structure and Transmission Characteristics of Disordered AlGaAs Nanowires Objective Method to model bandstructure of disordered nanowires Detailed understanding of transport by comparing bandstructure and transmission characteristics Approach Transmission: Non-equilibrium Green’s function method Bandstructure: Supercell calculation and zone-unfolding Results Transmission: noisy and reduced due to disorder Unfolded bands relate well to transmission Peaks in transmission due to localization Impact m* and Eg extracted from unfolded bands can be used in simple models such as top-of-the-barrier or effective mass device simulators Energy [eV] Transmission kx [π/a] Energy [eV] Transmission kx [π/a] Energy [eV] Slab Transmission Al Ga As 5 10 15 20 3 2 1 x [nm] y [nm] z [nm] AlGaAs – Boykin et al., IEEE TNANO 2007, SiGe – Kharche et al., JCE 2007

Outline Motivation Tight-Binding Approach to Model Atomic Scale Variations Summary of Results Valley Degeneracies in (111) Si Quantum Wells Valley-Splitting in (100) SiGe/Si/SiGe Quantum Wells Transport Characteristics of InAlAs Nanowires Ultra-Scaled InAs HEMTs Performance Analysis of Ultra-Scaled InAs HEMTs Modeling Approach Comparison to Experiments Scaling Considerations Summary of Contributions Outlook

Performance Analysis of Ultra-Scaled InAs FETs Objective Develop: a methodology to simulate ultra-scaled InAs FETs Benchmark: match experimental I-Vs for “large” devices Lg = 30 - 50nm Improve: device design for scaling down to 20nm node Results/Impact Good quantitative match to experiments Performance optimization of 20nm device InAs InAlAs InGaAs n+ Cap Source Drain InP etch stop Gate InP Substrate δ-doped layer Lg Sim. vs. Expt. Lg=20nm Vd=0.50 V Vd=0.05 V Performance optimization D.H. Kim, EDL 2008 Kharche et al., IEDM 2009

Outline Motivation Tight-Binding Approach to Model Atomic Scale Variations Summary of Results Valley Degeneracies in (111) Si Quantum Wells Valley-Splitting in (100) SiGe/Si/SiGe Quantum Wells Transport Characteristics of InAlAs Nanowires Ultra-Scaled InAs HEMTs Performance Analysis of Ultra-Scaled InAs HEMTs Modeling Approach Comparison to Experiments Scaling Considerations Summary of Contributions Outlook

Motivation: Why III-V HEMTs? III-V: Extraordinary electron transport properties and high injection velocities HEMTs: Very similar structure to MOSFETs except high-κ dielectric layer Excellent to Test Performances of III-V material without interface defects Every Year Devices with a Shorter Gate Length Introduced by del Alamo’s Group at MIT Excellent to Test Simulation Models Develop simulation tools and benchmark with experiments Predict performance of ultra-scaled devices 2007: 40nm 2008: 30nm D.H. Kim et al., EDL 29, 830 (2008)

Outline Motivation Tight-Binding Approach to Model Atomic Scale Variations Summary of Results Valley Degeneracies in (111) Si Quantum Wells Valley-Splitting in (100) SiGe/Si/SiGe Quantum Wells Transport Characteristics of InAlAs Nanowires Ultra-Scaled InAs HEMTs Performance Analysis of Ultra-Scaled InAs HEMTs Modeling Approach Comparison to Experiments Scaling Considerations Summary of Contributions Outlook

Device Geometry and Simulation Domain Intrinsic device Near gate contact Self consistent 2D Schrodinger-Poisson Electrons injected from all contacts Extrinsic source/drain contacts Series resistances RS and RD Simulation Domain: Intrinsic device Source Drain Extrinsic device Lg Source Drain Gate n+ Cap n+ Cap InP etch stop InAlAs δ-doped layer M. Luisier et al., IEEE Transactions on Electron Devices, vol. 55, p. 1494, (2008). InAs InGaAs InP Substrate R. Venugopal et al., Journal of Applied Physics, vol. 95, p. 292, (2004).

Outline Motivation Tight-Binding Approach to Model Atomic Scale Variations Summary of Results Valley Degeneracies in (111) Si Quantum Wells Valley-Splitting in (100) SiGe/Si/SiGe Quantum Wells Transport Characteristics of InAlAs Nanowires Ultra-Scaled InAs HEMTs Performance Analysis of Ultra-Scaled InAs HEMTs Modeling Approach Comparison to Experiments Scaling Considerations Summary of Contributions Outlook

Transfer Characteristics: Id-Vgs Material Parameters Parameter Initial Final parameter set 30 40 50 Lg [nm] 30, 40, 50 34.0 42.0 51.25 tins [nm] 4 3.6 3.8 4.0 m*ins 0.075 0.078 m*buf 0.041 0.043 ΦM [eV] 4.7 4.66 4.69 4.68

Output Characteristics: Id-Vds Conclusion: Good agreement for all Lg’s Less ballistic at Lg=50nm Use models and material parameters to design ultra-scaled devices (Lg=20nm)

Outline Motivation Tight-Binding Approach to Model Atomic Scale Variations Summary of Results Valley Degeneracies in (111) Si Quantum Wells Valley-Splitting in (100) SiGe/Si/SiGe Quantum Wells Transport Characteristics of InAlAs Nanowires Ultra-Scaled InAs HEMTs Performance Analysis of Ultra-Scaled InAs HEMTs Modeling Approach Comparison to Experiments Scaling Considerations Summary of Contributions Outlook

ΦM tins tInAs What can be changed? Gate geometry Channel thickness: tInAs Insulator thickness: tins Metal work function engineering: ΦM Better control of surface potential Gate leakage reduction and E-mode operation Lg=20nm Gate ΦM In0.52Al0.48As tins Source In0.53Ga0.47As Drain tInAs InAs

Parameters and Performances Summary (1) Gate geometry (2) Channel thickness (3) Insulator thickness (4) Metal work function Improved gate control Lower SS higher ION/IOFF Higher gate leakage Higher SS Lower ION/IOFF Gate leakage reduction Lower SS Higher ION/IOFF SS ION/IOFF 1 Lg=20nm 3 4 4 2 2 1 3

HEMT Simulator on nanoHUB.org OMEN_FET: HEMTs, Single- and Double-Gate devices Electron transport in Si and III-V Current Flow Visualization http://nanoHUB.org/tools/omenhfet Run your own simulations!

Outline Motivation Tight-Binding Approach to Model Atomic Scale Variations Summary of Results Valley Degeneracies in (111) Si Quantum Wells Valley-Splitting in (100) SiGe/Si/SiGe Quantum Wells Transport Characteristics of InAlAs Nanowires Ultra-Scaled InAs HEMTs Performance Analysis of Ultra-Scaled InAs HEMTs Modeling Approach Comparison to Experiments Scaling Considerations Summary of Contributions Outlook

Summary of Contributions (1) (111) Si quantum wells: Explained 2-4 valley degeneracy breaking (APL 2009) Miscut (100) SiGe/Si/SiGe quantum wells: Provided qualitative and quantitative understanding of valley splitting (APL 2007) Expected Observed Cause: Surface miscut Si SiGe Alloy disorder Si SiGe Rough steps No disorder

Summary of Contributions (2) AlGaAs and SiGe nanowires: Provided understanding of transmission coefficients by employing zone-unfolding method (TNANO 2007, JCE 07) InAs HEMTs: Demonstrated quantitative agreement between experiments and simulations. Performance optimizations for ultra-scaled HEMTs (IEDM 09) Energy [eV] Transmission kx [π/a] Extrinsic device Simulation Domain: Intrinsic device Lg=20nm Vd=0.50 V Vd=0.05 V Sim. vs. Expt. Performance optimization

Outline Motivation Tight-Binding Approach to Model Atomic Scale Variations Summary of Results Valley Degeneracies in (111) Si Quantum Wells Valley-Splitting in (100) SiGe/Si/SiGe Quantum Wells Transport Characteristics of InAlAs Nanowires Ultra-Scaled InAs HEMTs Performance Analysis of Ultra-Scaled InAs HEMTs Modeling Approach Comparison to Experiments Scaling Considerations Summary of Contributions Outlook

Outlook (1) Valley degeneracies in (110) Si QWs Both 4 and 2 fold valley degeneracies are reported in experiments Flat (110) => 2 fold degenerate Miscut (110) => 4 fold degenerate Effect of Ge concentration on valley splitting in (100) SiGe/Si/SiGe QWs Disorder in SiGe reduces valley splitting and sensitivity to Ge concentration U [eV] z [nm] Si QW SiGe barrier ΔEC 2.17 nm 25.53 nm VCA SiGe Random alloy SiGe

Outlook (2) Supercell approach and zone-unfolding III-V MOSFETs Electronic structure of rough nanowires and QWs Hole transport in SiGe pMOS devices III-V MOSFETs InAs InAlAs n+ Cap Source Drain InP etch stop Gate InGaAs δ-doping Schottky gate MOS gate Intel, IEDM 2009

Acknowledgements Advisors: Committee members: Professor Gerhard Klimeck Professor Timothy Boykin Committee members: Professor Mark Lundstrom Professor Supriyo Datta Professor Ronald Reifenberger Dr. Mathieu Luisier Klimeck Group Members and Labmates

Backup Slides

Gate Geometry and Gate Leakage Current 1 (a) 3 2 (b) 1) Include Series Resistances 2) Include Gate Leakage Current 3) Include the Proper Gate Geometry Flat (a) or Curved (b) Gate leakage reduced in curved gate device

InAs and InAlAs Layer Thickness IOFF increases gate leakage InAs Channel Scaling: Better electrostatic control lower SS larger ION/IOFF ratio Increase of transport m* reduced vinj, higher Ninv => higher ION Increase of gate leakage current ION/IOFF ratio saturates InAlAs Insulator Scaling: Better electrostatic control (due to larger Cox) Increase of gate leakage current larger IOFF larger SS smaller ION/IOFF ratio

InAs (Channel) Layer Thickness InAs Channel Scaling: Better electrostatic control lower SS larger ION/IOFF ratio Increase of transport m* reduced vinj, higher Ninv => higher ION Increase of gate leakage current ION/IOFF ratio saturates IOFF increases Gate Source In0.53Ga0.47As Drain tInAs InAs In0.52Al0.48As

InAlAs (Insulator) Layer Thickness InAlAs Insulator Scaling: Better electrostatic control (due to larger Cox) Increase of gate leakage current larger IOFF larger SS smaller ION/IOFF ratio gate leakage Gate tins Source In0.53Ga0.47As Drain InAs In0.52Al0.48As

Work Function Engineering Work Function Increase: Shift towards enhancement mode Decrease of gate leakage current Allows for thinner insulator layer steeper SS larger ION/IOFF ratio

Gate Leakage Mechanism Electrons tunnel from gate into InAs channel Tunneling barriers InAlAs and InGaAs Position dependent barriers Current crowding at edges (due to lower tunneling barriers) Barriers modulated by ΦM ΦM

Work Function Engineering (2) ΦM =4.7 eV ΦM =5.1 eV Characteristics: Same Gate Overdrive same thermionic current (source to drain) Gate Fermi levels shifted by ΔΦM different tunneling barrier height ΦM =4.7 eV tunnel through InAlAs only larger Ig ΦM =5.1 eV tunnel through InAlAs and InGaAs lower Ig