Testing And Testable Design of Digital Systems بسم الله الرحمان الرحيم Testing And Testable Design of Digital Systems College of Electrical Engineering Iran University of Science and Technology Karim Mohammadi Faut-Tolerant Digital System Design week-1

Course Outline Part I: Introduction Basic concepts and definitions (Chapter 1) Test process and ATE (Chapter 2) Test economics and product quality (Chapter 3) Fault modeling (Chapter 4) VLSI Test: Lecture 1

Course Outline (Cont.) Part II: Test Methods Logic and fault simulation (Chapter 5) Testability measures (Chapter 6) Combinational circuit ATPG (Chapter 7) Sequential circuit ATPG (Chapter 8) Memory test (Chapter 9) Analog test (Chapters 10 and 11) Delay test and IDDQ test (Chapters 12 and 13) VLSI Test: Lecture 1

Course Outline (Cont.) Part III: DFT Scan design (Chapter 14) BIST (Chapter 15) Boundary scan and analog test bus (Chapters 16 and 17) System test and core-based design (Chapter 18) VLSI Test: Lecture 1

References: 1 - Digital Systems Testing and Testable Design Miron Abramovici Melvin A. Breuer Arthur D. Friedman IEEE PRESS ISBN 0-7803-1062-4 2 - Fault-Tolerant Computer System Design Dhiraj K. Pradhan Prentice Hall

3 - Essentials of Electronic Testing For Digital, Memory and Mixed- Signal VLSI Circuits Michael L. Bushnell Vishwani D. Agrawal Kluwer Academic Publisher Boston/ Dordrecht/London 4- Appendix C : Books On Testng Faut-Tolerant Digital System Design week-1

Lecture 1 Introduction VLSI realization process Verification and test Ideal and real tests Costs of testing Roles of testing A modern VLSI device - system-on-a-chip Course outline Part I: Introduction to testing Part II: Test methods Part III: Design for testability VLSI Test: Lecture 1

VLSI Realization Process Customer’s need Determine requirements Write specifications Design synthesis and Verification Test development Fabrication Manufacturing test Chips to customer VLSI Test: Lecture 1

Definitions Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect. VLSI Test: Lecture 1

Testing During VLSI Development Design verification targets design errors Corrections made prior to fabrication Remaining tests target manufacturing defects A defect is a flaw or physical imperfection that can lead to a fault Design Verification Wafer Test Final Testing Package Test Design Specification Design Fabrication Quality Assurance Packaging Flaw عیب imperfection نقص Quality Assurance تضمین کیفیت

Design Verification Different levels of abstraction during design CAD tools used to synthesize design from RTL to physical level Simulation used at various level to test for Design errors in behavioral or RTL Design meeting system timing requirements after synthesis Design Specification Behavioral (Architecture) Level Register-Transfer Level Logical (Gate) Level Physical (Transistor) Level Abstraction چکیدگی ؛ انتزاع؛تجرید ؛ تجرد Synthesis ترکیب

Electronic System Manufacturing A system consists of PCBs that consist of VLSI devices PCB fabrication similar to VLSI fabrication Susceptible to defects Assembly steps also susceptible to defects Testing performed at all stages of manufacturing Bare Board Test Board Test System Test Unit Test PCB Fabrication PCB Assembly System Assembly Unit Assembly Susceptible مستعد پذیرش؛ حساس

Verification vs. Test Verifies correctness of manufactured hardware. Two-part process: 1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardware Test application performed on every manufactured device. Responsible for quality of devices. Verifies correctness of design. Performed by simulation, hardware emulation, or formal methods. Performed once prior to manufacturing. Responsible for quality of design. VLSI Test: Lecture 1

Problems of Ideal Tests Ideal tests detect all defects produced in the manufacturing process. Ideal tests pass all functionally good devices. Very large numbers and varieties of possible defects need to be tested. Difficult to generate tests for some real defects. Defect-oriented testing is an open problem. VLSI Test: Lecture 1

Real Tests Based on analyzable fault models, which may not map on real defects. Incomplete coverage of modeled faults due to high complexity. Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss. Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level. VLSI Test: Lecture 1

Testing as Filter Process Mostly good chips Good chips Prob(pass test) = high Prob(good) = y Fabricated chips Prob(pass test) = low Prob(fail test) = low Mostly bad chips Defective chips Prob(bad) = 1- y Prob(fail test) = high VLSI Test: Lecture 1

Number of acceptable parts Yield= Total number of parts fabricated Number of faulty parts passing final test Defect Level= Total number of parts passing final test Number of detected faults Fault coverage= Total number of faults Fault detection effeciency= Number of detected faults Total number of faults−number of undetectable faults

Costs of Testing Design for testability (DFT) Chip area overhead and yield reduction Performance overhead Software processes of test Test generation and fault simulation Test programming and debugging Manufacturing test Automatic test equipment (ATE) capital cost Test center operational cost VLSI Test: Lecture 1

Design for Testability (DFT) DFT refers to hardware design styles or added hardware that reduces test generation complexity. Motivation: Test generation complexity increases exponentially with the size of the circuit. Example: Test hardware applies tests to blocks A and B and to internal bus; avoids test generation for combined A and B blocks. Logic block A block B PI PO Test input output Int. bus VLSI Test: Lecture 1

Purpose of Manufacture Testing Verify Manufacture of Circuit Improve System Reliability Diminish System Cost Cost of repair goes up by an order of magnitude each step away from fab line 0.5 5 50 500 IC Test Board System Warranty Repair 10 1 100 1000 Cost per fault (Dollars) Cost – Rule of 10 It costs 10 times more to test a device as we move to higher levels in the product manufacturing process VLSI Test: Lecture 1

Testing and Quality * Quality of shipped part is a function of Shipped Parts ASIC Testing Fabrication Yield: Quality: Fraction of Defective parts good parts per million (DPM) Rejects * Quality of shipped part is a function of yield Y and the test (fault) coverage T. VLSI Test: Lecture 1

Fault Coverage * Fault coverage T is the measure of the ability of a set of tests to detect a given class of faults that may occur on the device under test. T = # of detected faults of possible faults VLSI Test: Lecture 1

Defect Level * Defect Level, DL is the fraction of the shipped parts that are defective. DL = 1 - Y (1- T ) Y: yield T: fault coverage VLSI Test: Lecture 1

Relating Defect Level to Fault Coverage 10 20 30 40 50 60 70 80 90 100 .1 .2 .3 .4 .5 .6 .7 .8 .9 1 Y=.99 Y=.90 Y=.75 Y=.50 Y=.25 Y=.10 Y=.01 Y = Yield Fault Coverage, T (%) DL = 1 - Y (1-T) VLSI Test: Lecture 1

Defect Level, Yield and Fault Coverage 50% 90% 67,000 75% 28,000 10,000 95% 5,000 99% 1,000 99.9% 100 Yield Fault Coverage DPM VLSI Test: Lecture 1

Scan Flip-Flop (SFF) D Master latch Slave latch TC Q MUX Q SD CK Logic overhead MUX Q SD CK D flip-flop VLSI Test: Lecture 23

Adding Scan Structure Not shown: CK or MCK/SCK feed all SFFs. PI PO SCANOUT Combinational logic SFF SFF TC or TCK Not shown: CK or MCK/SCK feed all SFFs. SCANIN VLSI Test: Lecture 23

System Test Logic Copyright 2001, Agrawal & Bushnell Teat data Input Serial Input to boundry register Test Clock For boundry Scan Test Data Otput Test Mode Selet signal Asyncronous Reset For Boundry Scan Test acess port : finite state machine that recognizes the boundry scan communication protocol and controls the operation through internal signals Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

DFT Standards IEEE Std. 1149. 1 IEEE Std. 1149. 1b IEEE Std. 1149 DFT Standards IEEE Std. 1149.1 IEEE Std. 1149.1b IEEE Std. 1149.5 IEEE Std. 1029.1 MIL-HDBK-XX47 VLSI Test: Lecture 1

IEEE Std. 1149.1 - Test Access Port and Boundary-Scan Architecture Defines the architecture of the TAP and Boundary Scan cells IEEE 1149.1b - defines the Boundary-Scan Description Language (BSDL) IEEE Std. P1149.2 - Extended Serial-Digital Interface Standard Defines a scheme that supports board-level interconnect testing and internal-scan testing of components IEEE Std. P1149.3 - Real Time Test Bus Standard Proposed to define standards for real-time testability bus (work discontinued) VLSI Test: Lecture 1

IEEE Std. P1149.4 - Mixed-Signal Test Bus Standard Proposed to extend the concept of boundary-scan to analog and mixed signal devices IEEE Std. P1149.5 - Module Test and Maintenance Bus Standard Defines specifications for a serial test and maintenance bus for systems with two or more modules plugged into a backplane IEEE Std. 1029.1 - Waveform and Vector Exchange Specification (WAVES) Defines standard for VHDL description of stimulus vectors and responses MIL-HDBK-XX47 Testability Analysis Handbook VLSI Test: Lecture 1

Cost of Manufacturing Testing in 2000 0.5-1.0GHz, analog instruments,1,024 digital pins: ATE purchase price = $1.2M + 1,024 x $3,000 = $4.272M Running cost (five-year linear depreciation) = Depreciation + Maintenance + Operation = $0.854M + $0.085M + $0.5M = $1.439M/year Test cost (24 hour ATE operation) = $1.439M/(365 x 24 x 3,600) = 4.5 cents/second VLSI Test: Lecture 1

Roles of Testing Detection: Determination whether or not the device under test (DUT) has some fault. Diagnosis: Identification of a specific fault that is present on DUT. Device characterization: Determination and correction of errors in design and/or test procedure. Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT. VLSI Test: Lecture 1

A Modern VLSI Device System-on-a-chip (SOC) DSP core RAM ROM Transmission medium Data terminal Inter- face logic Mixed- signal Codec Figure 18.5 (page 605) VLSI Test: Lecture 1

چالشهاي آزمون SOC ها ُ گستردگي و تنوع در طراحي و تحقق فرآيند آزمون كنترل‌پذيري، رويت‌پذيري و دسترسي آزمون حجم اطلاعات آزمون، ظرفيت كانال آزمونگر، مدت زمان آزمون بلوك‌‌هاي بنيادي نامتجانس انجام آزمون در سرعت كاري اتلاف توان در فرآيند آزمون