ENG3050 Embedded Reconfigurable Computing Systems LAB #5: Profiling and Adding an IP to the Arm Processor on Zync FPGA using Vivado & SDK Tools ENG3050: Lab #5

Introduction Vivado is a design suit for Embedded system design. With Vivado you can create complex applications that take advantage of both: The processing system (PS) in the form of ARM Cortex-A9 and also, The programmable logic to add hardware accelerators that can be attached to the PS in a Hardware/Software co-design fashion. ENG3050: Lab #5

Lab Objectives Enhance your knowledge about Xilinx Vivado design software suit. Guide you through the process of creating a simple ARM Cortex-A9 based processor design targeting the ZedBoard. Use the Software Development Kit (SDK) to create simple applications that run on the processor and further profile the applications. Finally, you will learn how to add a custom IP to further accelerate applications. ENG3050: Lab #5

Zync-7000 SoC The PS/PL The Zedboard uses the Xilinx Zync-7000 FPGA The Zynq-7000 AP SoC architecture consists of two major sections PS: Processing system Dual ARM Cortex-A9 processor based Multiple peripherals Hard silicon core PL: Programmable logic Uses the same 7 series programmable logic Artix™-based devices: Z-7010, Z-7015, Z-7020 (high-range I/O banks only) Kintex™-based devices: Z-7030, Z-7035, Z-7045, Z-7100 (mix of high-range and high-performance I/O banks)

Zynq-7000 AP SoC Block Diagram

Vivado Components Vivado/IP Integrator Software Development Kit (SDK) Design environment for configuration of PS, and hardware design for PL Hardware Platform (xml) Platform, software, and peripheral simulation Vivado logic analyzer integration Software Development Kit (SDK) Project workspace Hardware platform definition Board Support Package (BSP) Software application Software debugging Hardware Design HW/SW Simulation Software Design HW/SW Debug

Vivado View Customizable panels A: Project Management B: IP Integrator C: FPGA Flow D: Layout Selection E: Project view/Preview Panel F: Console, Messages, Logs A B E C F

Export Hardware Design to SDK Software development is performed with the Xilinx Software Development Kit tool (SDK) An XML description (.hdf Hardware Description file) of the hardware is imported in the SDK tool The hardware platform is built on this description Only one hardware platform for an SDK project SDK will then associate user software projects to hardware

SDK Workbench Views C/C++ project outline displays the elements of a project with file decorators (icons) for easy identification C/C++ editor for integrated software creation Code outline displays elements of the software file under development with file decorators (icons) for easy identification Problems, Console, Properties views list output information associated with the software development flow 1 2 3 4

Embedded System Design using Vivado and SDK 1. Launch Vivado 2. Create Block Design 8. Create Top-Level HDL 9. Add Constraints (file) 10. Generate Bitstream => .bit 11. Export hardware to SDK 3. Add PS7 4. Configure PS settings 5. Run Block Automation 6. Add and configure IPs 7. Run Connection Automation IP Integrator 12. Create Board Support Package 13. Create or add Software Project 14. Build application => .elf SDK Vivado 15. Program bitstream & .elf into Zynq ZedBoard

Requirements First you will go through two tutorials: Tutorial #1: Building an Embedded Processor System on a Xilinx Zync FPGA (Profiling) by SOE. Tutorial #2: Creating a Custom IP Block in Vivado using ZedBoard by SOE. You will then be asked to profile an application (see website and lab handout). You will also replace the Multiplier IP introduced in Tutorial #2 with an Adder ENG3050: Lab #5