HV-MAPS Designs and Results I

Introduction HVCMOS detectors are depleted active segmented detectors implemented in a CMOS process The sensor element is an n-well diode in a p-type substrate The electronics is placed inside the n-well sensor electrode. High voltage is used to deplete a part of the substrate. The main charge collection mechanism is drift of the charge signal from the depleted region HVCMOS NMOS PMOS N-well Depleted P-substrate

Substrate resistivity HVCMOS can be implemented in standard CMOS technologies These technologies have substrate resistances of 10 to 20 Ωcm. The HVCMOS structure can be improved by taking a substrate of higher resistance (for instance 100 – 1000 Ωcm) instead of the standard one. (Non-standard CMOS process) The transistors will be not affected since they are placed in n-wells and not is in the substrate itself Particle Particle Deep-n-well Deep-n-well +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

Sensor architectures - monolithic Depending on proposed application we have several sensor architectures. For Mu3e and strips we have the monolithic sensors. Active pixels contain usually only the analog circuits like the charge sensitive amplifier. The pixels are connected to the readout cells placed at the chip periphery. Every pixel has its readout cell. These RO cells do zero-suppression and generate hit-addresses. RO-cells contain hit buffers (Mu3e) of hit multiplexer (strips) Instead of analog pixels we are investigating the use the pixels with comparators that generate pixel addresses and transmit the addresses to the periphery. Row/Col Addr + TS One RO cell /pixel Pixel contains a charge sensitive amplifier CSA

MuPixel 92µm

MuPixel (RO-cell) 46 µm Comparator Address ROM TS DRAM 7µm DAC and SRAM Coupling capacitor CMOS digital part

MuPixel test beam Test-beam measurement February 2014 DESY Performed by our colleagues from Institute for Physics

Sensor architectures - hybrid For ATLAS pixels and CLIC we have developed the smart sensor concept We use the existing readout chips (FEI4 in the case of ATLAS and CLIC-pix in the case of CLIC) for the readout of HVCMOS sensors. Advantages in comparison with the standard hybrid sensors: The signal transmission between sensor- and readout chip can be done capacitively, without bumps Capacitively coupled pixel detectors - CCPD Another advantage can be increased spatial resolution. Many smaller pixels can be coupled to one channel of the readout chip Readout pixel Size: 50 µm x 250 µm TOT = sub pixel address Different pulse shapes + Size: 33 µm x 125 µm

Test beam results University of Geneva group has done a test beam measurement in November 2014 99.5% detection efficiency with the latest prototype (left). (Pixels with comparators.) The measurement has been done under suboptimal conditions – the bias voltage was only 12V.

Test beam results Several chips irradiated with neutrons at Jozef Stefan institute in Ljubljana. Detection efficiency with an irradiated chip (fluence 1015 neq) 96% (right) Bias voltage was reduced – 35V

HVMAPS for ATLAS

Sensor types Type A – HVCMOS Type B – HRCMOS HVCMOS CMOS PMOS must be isolated with a deep P-well N-Well N-Well Variant 1 PMOS not isolated Variant 2 PMOS isolated with a deep P-well N-Well CMOS N-Well CMOS

Readout types: in-pixel hit buffer (“column drain”) Concept: Every pixel has its own readout cell, placed on the chip periphery CSA Hit flag Comparator Priority scan logic RAM/ROM Pixel contains a charge sensitive amplifier and optionally a discriminator with a threshold tune DAC Comparator and Thr tune DAC Read Time stamp Data bus Readout cell function – time stamp is stored when hit arrives Hit data are stored until the readout Priority logic controls the readout order RO cell size in 0.18um ~ 7um x 50um (With comparator and thr-tune DAC) Without comparator: 7um x 25um Example: Pixel size 250um x 50um Chip size: ~ 2cm x 2cm Number of pixels: 80 x 400 Size of periphery with comparators: 2cm x 560um (2.8 %) Size of periphery without comparators: 2cm x 280um (1.4%) Output data (8b TS + 16b Address) x 10 hits/BC = 240 total Data rate ~ 10Gb/s (assumed 10 hits/BC/4cm2) Efficiency issue: dead time per pixel after hit ~ 200ns One RO cell /pixel RowAddr + TS Shift register

Readout types: in-pixel trigger Concept: Every pixel has its own readout cell, placed on the chip periphery CSA Triggered hit flag Comparator Hit flag RAM/ROM Priority scan logic Pixel contains a charge sensitive amplifier and a discriminator with threshold tune DAC Time stamp Delayed TS and trigger Read Data bus One RO cell /pixel Readout cell function – time stamp is stored when hit arrives The stored time stamp is compared with the current time stamp If trigger arrives with the correct latency, the triggered hit flag is set Priority logic controls the readout order Four pixels share four trigger units Efficiency issue – when more than four hits within L1 delay in four pixels Estimated cell size in 0.18um without comparator ~ 7um x 50um Example: Pixel size 50um x 250um Chip size: ~ 2cm x 2cm Number of pixels: 80 x 400 Size of periphery without comparator: 2cm x 560um (2.8 %) Output data (8b TS + 16b Address) x 10 hits/L1 – rate 24Mbit/s RowAddr + TS Shift register

In-pixel hit processing with the RO placed in active area Concept: Every pixel has its own readout cell, placed in the pixel itself (active area) Triggered hit flag Smart diode implementation Hit flag RAM/ROM CSA Comparator Priority scan logic N-Well Time stamp Delayed TS and trigger Read Data bus The implementation of the whole readout in active region requires deep P-Well No digital periphery required Crosstalk is an issue Limited technology choice - Lfoundry, ESPROS, X-FAB

In-pixel hit processing with the RO placed in active area HVMAPS implementation N-Well N-Well N-Well

In-pixel hit buffer

in-pixel hit buffer

in-pixel hit buffer

in-pixel hit buffer

in-pixel hit buffer

in-pixel hit buffer

Constant-delay-multiplexing B C D Output 1 Output 2

Constant-delay-multiplexing B C D Output 1 Output 2

Constant-delay-multiplexing 1 2 A B C D Output 1 Output 2

Constant-delay-multiplexing A 1 B 2 C D Output 1 A Output 2 B

Constant-delay-multiplexing B C D Output 1 Output 2

Constant-delay-multiplexing B C D Output 1 Output 2

Constant-delay-multiplexing 1 A B C D Output 1 Output 2

Constant-delay-multiplexing 1 A B C D Output 1 C Output 2

Constant-delay-multiplexing B C D Output 1 Output 2

Constant-delay-multiplexing B C D Output 1 Output 2

Constant-delay-multiplexing 1 2 A B C D Output 1 Output 2

Constant-delay-multiplexing 1 2 A B C D Output 1 A Output 2 D

Constant-delay-multiplexing B C D Output 1 Output 2

Constant delay scheme CSA Comparator Pixel contains a charge sensitive amplifier and a discriminator with threshold tune DAC 2x7bit address Readout cell function – hit address with duration one time stamp is generated Hit multiplexer can cope with 2 hits per 80 pixels row or 18 simultaneous hits per matrix Efficiency issue – more than 18 hits/BC/matrix (10 hits in average) Estimated cell size in 0.18um without comparator ~ 7um x 25um Example: Pixel size 250um x 50um Chip size: ~ 2cm x 2cm Number of pixels: 80 x 400 Size of periphery without comparator: 2cm x 560um (1.4 %) Output data (16b Address) x 18 hits/BC = 288 total ~ rate 11Gbit/s 18 x 16bit address

Schemes with small periphery

Schemes with small periphery/in-pixel binary address CSA Address ROM Comparator hit s A sr ff Address Hit Pixel Ck hitSync n Example: Pixel size 250 um x 50 um Chip size: ~ 2cm x 2cm Number of pixels: 80 x 400 9 address lines/column, 720 total Efficiency issue – more than one hit per pixel column/BC EOC buffers

Schemes with small periphery/in-pixel binary address CSA Address ROM Comparator hit s A sr ff Address Hit Pixel Ck hitSync EoC buffer EoC buffer 25ns clock n Write prio. logic TS EOC buffers Read prio. logic Full flag Data In FIFO Hit RAM Address Hit TS Shift reg. Data bus Read

Schemes with small periphery/in-pixel projection address CSA Address ROM Comparator hit s sr ff HitX,HitY Pixel Ck hitSync EOC buffers Example: Pixel size 250 um x 50um Chip size: ~ 2cm x 2cm Number of pixels: 80 x 400 Number of segments 5 Number of primary address lines: 320/segment = 20/column = 1.6k Total The scheme can cope with larger number (~5) of simultaneous hits/80x80 pixel segment

Schemes with small periphery/in-pixel projection address Example: Pixel size 250 um x 50um Chip size: ~ 2cm x 2cm Number of pixels: 80 x 400 Number of segments 5 Number of primary address lines: 320/segment = 20/column = 1.6k Total The scheme can cope with larger number (~5) of simultaneous hits/80x80 pixel segment Orthogonal: 80 x 2 80 x 2 diagonal

Small pixels

Schemes with small periphery/in-pixel binary address CSA Address ROM Comparator hit s A sr ff Address Hit Pixel Ck hitSync n Example: Pixel size 40um x 40um Chip size: ~ 2cm x 2cm Number of pixels: 500 x 500 16 address lines/column, 8k total EOC buffers

Schemes with small periphery/in-pixel projection address Example: Pixel size 40um x 40um Chip size: ~ 2cm x 2cm Number of pixels: 512 x 512 Number of segments 8 x 8 Number of primary address lines: 256/segment = 32/column = 16k Total Orthogonal: 64 x 2 64 x 2 diagonal