1. CAM in L1 pixel trigger architecture
09/19/2016, Bergamo

2. HL-LHC Pixel ROC with ROI trigger R/O
(David Christian: July 14, 2016))
Hit storage in pixel array; data passed to periphery only if there is a trigger.
Minimum amount of logic in pixel array; all complexity associated with ROI trigger is in chip periphery.
Trigger = code (full or ROI) + crossing number (max latency, but no requirement of set latency).
Hit anywhere in column (or other group of pixel groups) causes crossing # to be stored in a content addressable memory (CAM) in EOC; CAM address is stored in hit pixel group & associated with pulse height info for hit pixels in group.
Normal trigger causes full-chip CAM (see next bullet) to check for crossing # match & readout if match is found. If no match, then all EOC CAMs are checked; match in any causes full R/O.
ROI trigger causes full-chip CAM to check for crossing # match; if a match is found, data in ROI is read out from buffer & full chip data is retained. If no match, all EOC CAMs are checked for crossing # match & read out to EOC FIFO if match is found. FIFOs with data are drained into full-chip buffer & data in ROI is read out. Full chip data is retained & crossing # stored in CAM.
Max latency causes crossing # to be broadcast to full-chip CAM & all EOC CAMs to free up corresponding memory locations & forget hit info held in array.

3. HL-LHC Pixel ROC with ROI trigger R/O
Hit storage in pixel array; data passed to periphery only if there is a trigger.
Minimum amount of logic in pixel array; all complexity associated with ROI trigger is in chip periphery.
Trigger= code (full or ROI) + crossing number (max latency, but no requirement of set latency).
FULL trigger = « universal » trigger that is sent to all the detector components. It doesn’t address ROI.
ROI trigger = coming, for instance, from em-cluster, it’s used for L1-trigger study. (even called « e- trigger »).

4. HL-LHC Pixel ROC with ROI trigger R/O
Hit anywhere in column (or other group of pixel groups) causes crossing # to be stored in a content addressable memory (CAM) in EOC; CAM address is stored in hit pixel group & associated with pulse height info for hit pixels in group.
ROI TRIGGER
FULL TRIGGER
Questions:
What is stored in the EOCs CAM?
EOC CAM1
EOC CAM2
EOC CAM3
EOC CAM4
EOC CAM5
Crossing #
Pulse height ?

5. HL-LHC Pixel ROC with ROI trigger R/O
Normal trigger causes full-chip CAM (see next bullet) to check for crossing # match & readout if match is found. If no match, then all EOC CAMs are checked; match in any causes full R/O.
Questions:
What is stored in Full-Chip CAM?
Which type of connection between the 2 CAMs?
What kind of buffer for full-chip CAM?
FULL TRIGGER NO
YES
Match??
FULL-CHIP CAM
BUFFER
R/O
EOC CAM1
EOC CAM2
EOC CAM3
EOC CAM4
EOC CAM5
FIFO
L1 trigger

6. HL-LHC Pixel ROC with ROI trigger R/O
ROI trigger causes full-chip CAM to check for crossing # match; if a match is found, data in ROI is read out from buffer & full chip data is retained. If no match, all EOC CAMs are checked for crossing # match & read out to EOC FIFO if match is found. FIFOs with data are drained into full-chip buffer & data in ROI is read out. Full chip data is retained & crossing # stored in CAM.
Questions:
Are data drained into full-chip buffer for both 2 cases of match?
ROI TRIGGER NO
YES
Match??
FULL-CHIP CAM
BUFFER
R/O
Data drained
readout
EOC CAM1
EOC CAM2
EOC CAM3
EOC CAM4
EOC CAM5
FIFO
L1 trigger

7. HL-LHC Pixel ROC with ROI trigger R/O
Max latency causes crossing # to be broadcast to full-chip CAM & all EOC CAMs to free up corresponding memory locations & forget hit info held in array
Questions:
What does it means MAX latency?
Are both CAM buffers free up?
ROI TRIGGER
FULL-CHIP CAM
BUFFER
R/O
Data drained
EOC CAM1
EOC CAM2
EOC CAM3
EOC CAM4
EOC CAM5
FIFO
L1 trigger