1. KIT – Universität des Landes Baden-Württemberg und nationales Forschungszentrum in der Helmholtz-Gemeinschaft www.kit.edu Status of HVCMOS Developments for ATLAS Ivan Peric, Roberto Blanco, Felix Ehrler, Christian Krämer, Richard Leys, Rudolf Schimassek, Hui Zhang, … on behalf of University of Bern, Brookhaven National Laboratory, University of Geneva, University of Heidelberg, IFAE, KIT, Lancaster University, University of Liverpool, University of Tsukuba, ANL and UCSC

2. Pixel 20162 Overview CCPD in AMS H18 HVCMOS technology – test-beam results H35DEMO – design and measurement results Monolithic detectors submitted in August 2016 Future plans

3. Pixel 20163 CCPD in H18 HVCMOS – Test-Beam Results The CCPDv1 was submitted in November 2011. It is a small HVCMOS test sensor that can be glued to the FEI4 and readout capacitively. Since then we have had the 7 versions where we improved the circuits The list of improvements is V1 Basic design V2 Improved radiation hardness, a few linear transistors replaced with enclosed, better guard rings V3 CLIC matrix – small pixels V4 Time encoding pixels V5 Time walk compensating pixels V6 Chip version in aH18 process based in Austria V7 Chip version with improved guard ring for higher HV

4. Pixel 20164 CCPD in H18 HVCMOS – Test-Beam Results … CCPDv1CCPDv2CCPDv3CCPDv4 4mm CCPDv5 CCPDv6 CCPDv7

5. Pixel 20165 CCPD in H18 HVCMOS – Test-Beam Results The pixel size is 33um x 125um. The pixel structure is so called smart diode (HVCMOS). Pixel electronics is in the deep n-well. The deep n-well is used 1. as sensor and 2. as substrate for the electronics. The CCPD chips are done in a standard HVCMOS process- they are implemented on the standard substrate of 10 - 20 Ohm cm. The PMOS transistors are not isolated from the deep n-well. It is a 3 well process: P/Nwell, deep Nwell. Therefore, PMOS may produce crosstalk to sensor – however by clever design this crosstalk have been avoided. One example of clever design is the use of NMOS-only current mode logic gates instead of CMOS logic gates. The pixel contains CSA, comparator with threshold tuning and the output stage. The purpose of the output stage is described in the figure. We group three pixels in a group. The signals are multiplexed to one CCPD pad. The signal is transmitted capacitively to FEI4. The pixel position is encoded as amplitude or pulse width. + TOT = sub pixel address Readout pixel Size: 50 µm x 250 µm Size: 33 µm x 125 µm Different pulse shapes 3.3V -HV

6. Pixel 20166 The latest test beam result: We measure 99.7 % efficiency after neutron irradiation to 10 15 with the full matrix. The time resolution is excellent. About 84% of the tracks are within 25ns bin – nearly all within 50ns. 99.7% Thresh = 0.870V Bias Timing[25ns bins] % hits CCPD in H18 HVCMOS – Test-Beam Results 99.7% effi 99.7% efficiency 25ns

7. Pixel 20167 Main improvements vs. previous beam tests: The results are for the fastest pixel in the cluster. We usually integrate over 16BC, however all data are within 4BC. Every cluster have a fast hit within 2 BC For the irradiated samples the cluster size is basically 1 and the effect of selecting fastest hit in cluster is minimal Bias settings improved Improved test setup for low noise: Caribou board with regulators close to the DUT, use of LVDS and all grounding referenced locally to the telescope DUT support plate Sensor were kept at a stable 20C (unirradiated) or -22-25C (irradiated). Leakage current was kept under 1uA Trigger only on particles that are within around 7ns from the rising-edge of the FEI4 clock to simulate a synchronous beam like in the LHC (“Phase Busy” trigger) 2000e threshold for the FEI4 used - nominal Th for the CCPD was 0.88-0.8=0.08V CCPD in H18 HVCMOS – Test-Beam Results Timing[25ns bins] % hits 25ns 99.7% effi

8. Pixel 20168 Francesco Armando Di Bello The plots for the sample irradiated to 1.3e14 n eq /cm 2. No phase busy trigger implemented CCPD in H18 HVCMOS – Test-Beam Results

9. Pixel 20169 CCPD - plans We are planning a large version of the CCPD within an AMS H18 engineering run in November. Rework of the pixel position encoding planned. Pixel size from 25um x 25um to 50um x 250um

10. Pixel 201610 Development of Monolithic Sensor for ATLAS The first HVCMOS sensors were monolithic – see e.g. Vertex 2006 HVCMOS talk (10 years of HVCMOS) Monolithic = readout circuits are placed on chip so that zero suppression is done on sensor chip and the hit data (address time stamp) are sent digitally One example of HVCMOS monolithic sensor is the MuPixel I. Peric: A Monolithic Pixel Detector in High-Voltage Technology, Vertex 2006

11. Pixel 201611 Development of Monolithic Sensor for ATLAS Plan: From MuPix to „ATLASPix“ The first step: design of large ATLAS sensor that is implemented on HiRes substrates – the sensor is called H35DEMO. It was designed by KIT, Barcelona, Liverpool in a cheaper and larger technology H35. The second step is a large ATLAS monolithic sensor in finer technology. Here we have decided to try similar designs in two technologies – AMS H18 and LFA15

12. Pixel 201612 The Large Area Demonstrator Sensor H35DEMO CCPD, MuPix, H35DEMO 2.5cm CCPDMuPixH35DEMO

13. Pixel 201613 Development of Monolithic Sensor for ATLAS H35DEMO can be used as a monolithic detector and a CCPD. The area of about 1 x 2 cm contains the readout circuits that do zero suppression and generation of hit data packets – time stamp and address. Readout circuits are active during sensor exposure the crosstalk was not observed. The entire area 2.5cm x 2cm can be readout also by FEI4 that can be glued onto H35DEMO. Signal transmission can be capacitively or by bumps. It is a multi purpose sensor. Monolithic/CCPD matrix CCPD matrix

14. Pixel 201614 Development of Monolithic Sensor for ATLAS The pixel size is 50um x 250um. The design is radiation hard - on smaller prototypes in H35 we have shown the radiation tolerance of at least to 100MRad. (F. Ehrler, R. Blanco, R. Leys, and I. Peric, “High-voltage cmos detectors,” http://dx.doi.org/10.1016/j.nima.2015.09.004)

15. Pixel 201615 Development of Monolithic Sensor for ATLAS Analog power consumption is about 200mW / cm 2. On H35DEMO there are 3 matrix types, two monolithic/CCPD and 1 only CCPD. The monolithic matrices/CCPD are based on pixels with or without comparators, the pixels are connected to the readout cells placed on periphery. CCPD matrices use pixels without comparators. The readout cells have one or two thresholds for rejection of small hits. The pixel comparators have time walk correction. The sensor is implemented on 4 different substrates 20, 80, 200 Ohm cm and 1kOhm cm.

16. Pixel 201616 Development of Monolithic Sensor for ATLAS The sensor is working. We have tested the monolithic readout and the CCPD readout with FEI4. The latest result from tonight (SpS beam test – Mathieu Benoit):

17. Pixel 201617 Development of Monolithic Sensor for ATLAS The sensor is working. We have tested the monolithic readout and the CCPD readout with FEI4. The latest result from tonight:

18. Pixel 201618 Monolithic readout test at KIT. The sensor is irradiated with a source, hit data are taken. The beam spot can be noticed. Sensor on 80 Ohm cm. substrate was measured MIP is about 3700e (100V bias) noise is about 100e. (For 200 Ohm cm we have 4900e -> 59um at 140V bias) Development of Monolithic Sensor for ATLAS

19. Pixel 201619 Stefano Terzo (Institut de Física d’Altes Energies, Barcelona) Characterization of H35 test structures: 3x3 pixel structures Readout of the central pixel External pixels shorted together ρ=200 Ωcm – 1 kΩcm The Edge-TCT setup: Infra-red laser to produce localized e-h pairs Illumination from the edge to study the depletion depth Charge collection profile before irradiation ρ=200 Ωcm Central pixel signal at different depths (z): The FWHM of the charge collection profile in the middle of the pixel is taken as measure of the depletion depth Emanuele Cavallaro, IWORID 2016, Barcelona Development of Monolithic Sensor for ATLAS

20. Pixel 201620 Irradiation campaign at the JSI neutron reactor in Ljubljana: Now: 2e14 and 5e14 n eq cm -2 Planned up to 1e16 n eq cm -2 Acceptor removal effect for low resistivity substrate which leads to an increase of the depletion depth after irradiation Due to the low initial acceptor concentration in the high resistivity substrate the creation of stable acceptors dominates and the depletion depth decreases after irradiation Stefano Terzo (Institut de Física d’Altes Energies, Barcelona) Development of Monolithic Sensor for ATLAS

21. Pixel 201621 The sensor works as expected. More results, also on irradiated samples, will be presented In the next stage of our development we are implementing monolithic sensors for ATLAS in finer technologies. We have chosen two technologies AMS H18 and LFA15. Development of Monolithic Sensor for ATLAS

22. Pixel 201622 This August (2016) the HVCMOS collaboration (KIT, Barcelona, Geneva, Liverpool contributed to design) has submitted 6 matrices as five chips in LFA15 process (150nm) on different high resistive substrates. The total reticle size is 1 x 1 cm Similar designs will be realized in H18 technology and submitted beginning of October. Monolithic Sensors in LFA15 Process

23. Pixel 201623 This August (2016) the HVCMOS collaboration (KIT, Barcelona, Geneva, Liverpool contributed to design) has submitted 6 matrices as five chips in LFA15 process (150nm) on different high resistive substrates. The total reticle size is 1 x 1 cm Similar designs will be realized in H18 technology and submitted beginning of October. Monolithic Sensors in LFA15 Process 1cm

24. Pixel 201624 One matrix is a CCPD with small pixels (27.5um x 27.5um) that can be readout by the TimePix chip. (Next version for RD53 ROC is planned) The 4 matrices are the full featured monolithic matrices. They can be distinguished by the readout cell type, the pixel type and the pixel address multiplexing. The pixel contains CSA, comparator, edge detector, pulse stretcher and threshold tune circuit. Monolithic Sensors in LFA15 Process Unbuffered matrix Buffered matrix 1 Buffered matrix 2 Samplin g matrix TestStructuresTestStructures Buffered matrix 3 CCPD

25. Pixel 201625 One matrix uses untriggered readout – like in Mu3e or H35DEMO (based on FEI3) circuit. Monolithic Sensors in LFA15 Process Unbuffered matrix Buffered matrix 1 Buffered matrix 2 Samplin g matrix TestStructuresTestStructures Buffered matrix 3 CCPD

26. Pixel 201626 Four matrices use the novel triggered readout. This readout allows trigger delay of up to 25us. The readout is similar as in FEI4. A group of 8 or 16 pixels is attached to a readout trigger buffer block. The block has 4 cells that are identical. The hit OR stores the 8 local address bits into the first empty trigger buffer. After the trigger delay the buffer is either emptied (if no trigger) or marked for readout (if trigger is present). This scheme can cope with rather high occupancy. Number of buffer cells may be adjusted later. The size of the block (4 buffers) is only 40um x 100um. Monolithic Sensors in LFA15 Process Address generator Write controlRead control pixel1 pixelN Pixel address TSTSDelRdData (Address, TS) 4 Hit-Buffers Memory Hit Buffer 1 Hit Buffer 4 8 pixel2 Superpixel Pixel > 40um x 60um

27. Pixel 201627 Four matrices use the novel triggered readout. This readout allows trigger delay of up to 25us. The readout is similar as in FEI4. A group of 8 or 16 pixels is attached to a readout trigger buffer block. The block has 4 cells that are identical. The hit OR stores the 8 local address bits into the first empty trigger buffer. After the trigger delay the buffer is either emptied (if no trigger) or marked for readout (if trigger is present). This scheme can cope with rather high occupancy. Number of buffer cells may be adjusted later. The size of the block (4 buffers) is only 40um x 100um. Monolithic Sensors in LFA15 Process Address generator Write controlRead control pixel1 pixelN Pixel address TSTSDelRdData (Address, TS) 4 Hit-Buffers Memory Hit Buffer 1 Hit Buffer 4 8 pixel2 Superpixel Pixel > 40um x 60um Pixel Addr Superpixel Addr Time Stamp L1 Coincidence TriggeredHit Hit Buffer L1 Trigger Hit Reset

28. Pixel 201628 As mentioned the number of pixels in the block can be 8 – in this case every pixel has an address bit assigned. The pixel size is 40 x 100um. In the case of 16 pixels the pixel size is 40um x 60um and 16 – 8 address multiplexing is used. The pixel size for untriggered readout is 40 x 100um. Monolithic Sensors in LFA15 Process

29. Pixel 201629 One matrix uses the readout (untriggered) with the waveform sampling capability. The analog waveform is sampled with 8 – bit resolution, 6 times around the threshold crossing point. It can be 6 samples before the threshold crossing or 3 times before and 3 times after. The sampled voltages are immediately digitized (by 6 simple ADCs) and the digital values stored. Every pixel has its sampling blocks – we have 6 ADCs per pixel. The pixel size is 40 x 250um. With this novel sampling capability we would like increase the time resolution of HVCMOS sensors. Our measurements show that sampling of waveform several times before and after the signal onset can significantly improve the time resolution. The particle hit time can be determined by fit. Monolithic Sensors in LFA15 Process

30. Pixel 201630 We have implemented two pixel types. All but one matrix use the standard HVCMOS pixel – the “smart diode”. The electronics is placed in a large deep N-well. L-Foundry offers the deep P-well implant that allows isolation of PMOS from the sensors. Therefore we used the CMOS logic gates in pixel. One triggered matrix uses as comparison the “small diode” pixel type. Here the sensor diode is placed next to the readout electronics. The readout electronics is embedded in a deep PWell. The sensor diode can be biased with a high positive voltage. We expect that this pixel type have smaller capacitance and therefore better time resolution for equal power consumption. However it is unclear whether the radiation tolerance is a good as in the case of smart pixel and this will be verified. Monolithic Sensors in LFA15 Process Deep P well Smart diode Small diode

31. Pixel 201631 The chips will be produced in three months As mentioned similar designs will be realized in H18 technology and submitted beginning of October. The reticle size will be 2 x 2.5cm. Half of this run will be covered by the combined Mu3e ATLAS sensor. About a half will be the triggered ATLAS designs. One smaller reticle part will be the design that uses the isolated PMOS (fully CMOS) as in the case of LF. Monolithic Sensors in LFA15 Process

32. Pixel 201632 Test beam measurement with CCPD in H18 shows 99.7% efficiency, after irradiation (10 15 neq/cm2). About 84% of the tracks are within one time bin of 25ns, practically all within 50ns The measured sensor is a CCPDv4 (submitted May 2014 - not the last version) - glued to FEI4, the sensor is implemented on a low resistive wafer ~ 10 -20 Ohm without the deep pwell (no isolated PMOS), the process is AMS H18 (180nm) The first large area (5 cm 2 ) HVCMOS ATLAS demonstrator (H35DEMO) sensor in AMS H35 (350nm) process has been designed, produced and successfully tested (including beam test). The sensor have been produced on various high resistive wafers from 80 Ohm to > 1kOhm One half of the sensor has the monolithic readout that can be used in ATLAS. The readout is like in FEI3 - but without trigger buffers. All hit data - address and time stamps are sent out of the chip digitally. CCPD-readout with FEI4 as ROC is possible on the entire reticle area - which was successfully tested We have submitted in August 2016 five different monolithic sensor matrices for ATLAS with a total area of 1cm 2 in the LFoudry LFA15 process on various high resistive wafers. One matrix has the "untriggered readout" like FEI3 but without trigger buffers and similar like in Mu3e- or H35DEMO-sensors. This readout may be interesting for track trigger Three matrices have "triggered readout" that is based on similar trigger buffers as in FEI4. A trigger delay up to 25 us is possible. One matrix has the waveform sampling capability on pixel level Pixel sizes are from 40um x 250um (waveform sampling matrix) to 40 um x 60 um (triggered readout) Summary

33. Pixel 201633 There are two pixel types - first type is the HVCMOS structure (or smart diode). The other type is the structure with smaller diodes near electronics (small diode) that can be biased with a positive high voltage. Beside monolithic matrices a small-pixel CCPD matrix is implemented. The pixel size is 27.5um x 27.5um and the pixels can be readout by TimePix chip. Digital 4-1 multiplexing has been used. With this and similar CCPDs we want to test the possibility of low-cost small-pixel CCPD without the need of TSVs. Beginning of October we will submit large monolithic matrices within an engineering run in AMS H18 process. The reticle area will be about 5 cm 2, we will use two high resistive wafers types. The deep p-well will be tested too, this allows isolated PMOS. The matrices will be similar as in the LFoundry run, one matrix will be the radiation hard version of MuPix sensor that can be used for ATLAS as well. The tested digital readout rate of MuPixel is 1.6GBit/s in 180nm technology / link We are planning the submission of a large-area CCPD in AMS H18 process within an engineering run. The run is planned for beginning of 2017. Summary (2)