ETD meeting Electronic design for the barrel : Front end chip and TDC Forward PID electronics Next steps and millestones On behalf of PID group Christophe Beigbeder ETD meeting Sept 28 2010

Christophe Beigbeder ETD meeting PIF : PId Front End Chip Christophe Beigbeder ETD meeting Sept 28 2010

Christophe Beigbeder ETD meeting Requirements Time measurement : 100ps resolution max 1MHz background rate max 50ns double pulse resolution min Charge measurement dynamic range: ~10 to 20 8 bit Charge sharing Christophe Beigbeder ETD meeting Sept 28 2010 3

Proposal: CFD like + Charge integration Amplifier Sample & Hold Mux To ADC (Charge output) State Machine Synchronization with TDC data Pseudo CFD To TDC (SCATS chip) (discrimination signal) Christophe Beigbeder ETD meeting Sept 28 2010 4

CFD first simulation  Delay + Fraction  Gain + Integrators Fast comparator Classical CFD Proposed pseudo CFD Christophe Beigbeder ETD meeting H. Lebbolo – V. Tocut, SuperB Workshop, Frascati 09/2010 Sept 28 2010 5

PID Time measurement chip SCATS PID Time measurement chip Christophe Beigbeder ETD meeting Sept 28 2010

Christophe Beigbeder ETD meeting SCATS Designed on a existing basis: SNATS chip (linearity, resolution.. Match the PID req.) Expected dead time: 50ns (Matches the background input max frequency with a large safety factor) Instantaneous Dead time ~50ns Readout dead time Output Max speed~20 MHz Push the data Readout: Number of data words per event 4 3 2 1 Readout frequency per channel (All channels fired) 1,25 MHz 2,5 MHz 5 MHz Max readout frequency per channel (only one channel fired) 5 MHz 10 MHz 20 MHz Christophe Beigbeder ETD meeting Sept 28 2010

Front end Upgrade: current status scheme, simulation & layout : done Gray encoder Input channel inhibit scheme, simulation: done - layout : almost done Synchronizer (Matching between DLL & counter) Readout bus for the time registers : To be done Power supply rails optimization Input signal polarity selection LVDS receivers optimization Christophe Beigbeder ETD meeting Sept 28 2010

Readout Upgrade: current status Up to now: targeted in a Actel family FPGA in order to have a first post synthese evaluation of the performance . first level simulation Next steps readout behavior simulation with : 50 ns input dead time ( max expected performance ) 40 KHz readout frequency per channel 80 MHz deasy chain readout scrutation 150 KHz input noise with the good distribution law… Comportemental behavior model ( Verilog, C. VHDL ) Gate level simulation of one complete channel (fine + coarse TDC + readout) Integration of a 2nd gray counter ( SEU) Output fifo bypass in test mode Christophe Beigbeder ETD meeting Sept 28 2010

Christophe Beigbeder ETD meeting 16 channels / 2 words Christophe Beigbeder ETD meeting Sept 28 2010

Christophe Beigbeder ETD meeting Milestones RAM design: Ram size : 16 bits x 1 up to 4 words per event x 16 or 32 or … events per channel . The size has to be defined very soon to order the Ram to the vendor and start the design with Cadence design kit. available within a few days as soon as the configurations are chosen. Submission: Shared wafer in a dedicated run (with IRFFU): very end of Dec. 2010 ~ Jan 2011 or MPW run: beginning of Dec. 2010 1rst proto: 3 months later Christophe Beigbeder ETD meeting Sept 28 2010

Mother board for the Fblocks Christophe Beigbeder ETD meeting Sept 28 2010

Electronics for the CRT Christophe Beigbeder ETD meeting Sept 28 2010

Electronics for the CRT A synchronous sixteen channel acquisition system based on 8 two-channel WaveCatcher V5 boards and a controller board has been built for the Two Bar test at SLAC. The system works with a common clock. It is synchronized with the rest of the CRT Data acquisition is based on 480Mbits/s USB. Trig out CH0 CH1 Clk in Trig in USB Clk out Ext trig in 36dB Amp 8 Ext trig out Clock and control board 16 amplifiers DAQ PC From QTZ3 USB hub 8 USB WaveCatcher V5 Christophe Beigbeder ETD meeting Sept 28 2010

The USB WaveCatcher board V5 USB interface => 480Mbits/s Pulsers for reflectometry applications Reference clock: 200MHz => 3.2GS/s Board has to be USB powered => power consumption < 2.5W 1.5 GHz BW amplifier. µ USB Trigger input 2 analog inputs. DC Coupled. Clock input Trigger output +5V Jack plug Trigger fast discriminators SAM Chip Dual 12-bit ADC Cyclone FPGA Christophe Beigbeder ETD meeting Sept 28 2010

Clock and control board (2) USB interface => 480Mbits/s Zero jitter clock buffer Clock outputs Trig outputs µ USB Trigger Input (NIM) Trigger Output (NIM) +5V Jack plug Pulse output Trig inputs Reference clock: 200MHz Cyclone FPGA Christophe Beigbeder ETD meeting Sept 28 2010

Christophe Beigbeder ETD meeting …. An extension of the WaveCatcher system up to 16 channels has been realised (hardware + software) Cosmic data taking has already started on the two bars at SLAC, in coincidence with the CRT data (20th sept) A second 16-channel system for PMT test bench at LAL will be installed. A new 16-channel board, housing USB and high speed optical link, which will permit an easy upscaling of the number of channels is under study. Time measurements showed that even between different boards, there was still 10ps rms of time precision. Christophe Beigbeder ETD meeting Sept 28 2010

Christophe Beigbeder ETD meeting Experimental setup Christophe Beigbeder ETD meeting Sept 28 2010

Christophe Beigbeder ETD meeting Sept 28 2010

Christophe Beigbeder ETD meeting Sept 28 2010

FARICH prototype status Christophe Beigbeder ETD meeting Sept 28 2010

Christophe Beigbeder ETD meeting Sept 28 2010

Christophe Beigbeder ETD meeting Sept 28 2010

Christophe Beigbeder ETD meeting Next steps Christophe Beigbeder ETD meeting Sept 28 2010

Christophe Beigbeder ETD meeting Next Steps PID Barrel: PIF: ongoing design – 1rst prototype: middle of 2011 SCATS Submission: end of 2010 – 1rst prototype in April 2011. Mother board to be developped. TOF: Data taking continues … Characterization of the Mapmt in Jerry’lab. ( scanning with laser ) A new 16-channel board, housing USB and high speed optical link. A second 16-channel system for PMT test bench at LAL will be installed. FARICH: R&D goes on. Limited by the lack of electronic readout system Christophe Beigbeder ETD meeting Sept 28 2010