1. MCPPMT test bench at LAL D. Breton, L. Burmistov, J. Maalmi, V
MCPPMT test bench at LAL D.Breton, L.Burmistov, J.Maalmi, V.Puill (LAL Orsay)

2. Introduction
In view between others of SuperB PID TOF, we decided to mount a high speed PMT/SiPM test facility at LAL.
Therefore we built a second 16-channel acquisition crate identical to that used at SLAC on the CRT for the two bars
Same features except that the WaveCatcher boards have an internal gain of 10 and AC coupling => idea is to avoid buying amplifiers (6k€)
We also kept boards with DC coupling and gain 1 which allowed us to perform thorough time measurements which we had no time to perform before leaving for SLAC
Almost no difference was seen in time performance between gain 1 and gain 10 boards because all the elements implied therein are located behind where the gain is applied to the signal
This crate will first be used to read out 16 channels of MCPPMT (BURLE µ)

3. Introduction
Reminder of the technical challenge for the electronics: to keep the 10ps precision at the crate level …
The crate is based on 8 two-channel WaveCatcher V5 boards:
The system works with a common synchronous clock
There we take benefit of the external clock input of the WaveCatcher V5
It is self-triggered but it also has to be synchronized with its environment
Rate is low thus computer time tagging of events is adequate
Like the WaveCatcher, data acquisition is based on 480Mbits/s USB.

4. The USB Wave Catcher board V5
Reference clock: 200MHz => 3.2GS/s
Pulsers for reflectometry applications
1.5 GHz BW
amplifier.
Board has to be USB powered
=> power consumption < 2.5W
480Mbits/s USB interface
µ USB
Trigger
input
2 analog
inputs. DC
Coupled.
Clock
input
Trigger
output
+5V
Jack
plug
Trigger
discriminators
SAM Chip
Dual 12-bit ADC
Cyclone FPGA

5. Clock and control board (1)
From WaveCatchers
To WaveCatchers
From Laser
Trigger is done in coincidence mode : when the controller board detects a coincidence between an external trigger from laser and a hit in one of the sixteen channels

6. Clock and control board (2)
USB interface
=> 480Mbits/s
Zero jitter clock buffer
Clock outputs
Trig outputs
µ USB
Trigger
Input (NIM)
Trigger
Output (NIM)
+5V
Jack
plug
Pulse
output
Trig inputs
Reference clock: 200MHz
Cyclone FPGA

7. Full crate

8. Back of the crate

9. Acquisition software WaveCatcher software was extended to 16 channels
Each board can be set up independently
All channels can be displayed simultaneously
Run data can be split into multiple fixed size files (based on the user defined number of events) => permits run survey
A log file stores all messages generated during acquisition.
Now available: real time histogramming of inter-channel pulse time difference
With the laptop we use at SLAC, there was no way to run all the 9 boards on the same USB port
=> we had to share the boards between the 3 ports
Once the acquisition launched, USB looked stable (we could take very long runs => one week) but …
We recently discovered a problem with the PC internal USB buffers => events can be shifted between cards
=> a new software version with buffer purge has been released last week

10. MultiWaveCatcher Main Panel

11. MultiWaveCatcher: Board Panel

12. Description of the test setup
For the least jitter at short distance …
USB Wave Catcher
USB Wave Catcher
Open cable
Two pulses on the same channel
Two pulses on different channels or boards
=> with this setup, we can measure precisely the time difference between the pulses
independently of the timing characteristics of the generator!
HP81110/12/12
USB Wave Catcher
For other distances : high end generator
Two pulses generated with a programmable delay
Crosscheck with first method is performed at short distance

13. Characterization of multi-board system
2 pulses
Tr = Tf = 1.6ns
FWHM = 5ns
Δt = 0 ps
CFD ratio = 0.23
Slope at CF ~ 400mV/ns
Differential jitter = 5.78 ps rms
Density is very homogeneous

14. Effect of INL residue Δt = 2.5 ns
which is a half DLL length => differential residue of DLL INL is visible
Differential jitter = ps rms
Δt = 5 ns
which is a full DLL length => no differential residue of DLL INL is visible
Differential jitter = 9.79 ps rms

15. Effect of hit location in memory (Δt = 0)
Different Boards – Different Channels – random vs mastered location
7.64 ps rms
5.85 ps rms

16. Effect of hit location in memory (Δt = 10 ns)
Different Boards – Different Channels – random vs mastered location
13.14 ps rms
12.37 ps rms

17. Time performance of multi-board system
Mean differential jitter is of about 12ps rms which corresponds to 8.5 ps rms of equivalent time precision per pulse

18. Main elements of the PM test bench
BURLE Planacon XP85012 – 25 µm - 64 ch
Simple HT scheme
We grouped the pixels
into 16 groups of 4
Equalization of
the line lengths
for each group of
4 pixels

19. First basic setup

20. MCPPMT cabled in his test box

21. Light injection

22. First photons on the 16 channels

23. Moving toward the scanning setup (1)

24. Moving toward the scanning setup (2)

25. Moving toward the scanning setup (3)

26. Plot de Leonid Preliminary results
We performed a first fast scan of the PM
Threshold were not set very properly (lack of time)
Example of an horizontal crossing efficiency plot
Plot de Leonid mm

27. SAMLONG Chip 1024 pts - 3.2 GS/s 2 Channels
16-channel WaveCatcher
SAMLONG Chip 1024 pts GS/s 2 Channels
Dual 12 bits
ADC
4 Analog Input
Trigger In/out
FPGA
VME Format
USB 480 Mbits/s
Optical fiber output
Based on the very encouraging results of the 16-channel crate, we decided to start the design of a 16-channel WaveCatcher board
This board will be compatible with both SAM (256 cells/ch) and SAMLONG (1024 cells/ch)
The board can be synchronized externally => possibility to scale the system up to 320 channels in a crate
The first prototype will be available in April 2011

28. Conclusion
We built a second 16-channel USB Wave Catcher crate for our new MCPPMT/SiPM scanning setup at LAL.
This allowed us to perform thorough measurements on the electronics, which we had no time to do before the first crate left for SLAC in September
Timing measurements showed a stable single pulse resolution < 10 ps rms
The crate has been associated to a BURLE 25µ MCPPMT and mounted on the scanning setup
This allowed us to solve a serious USB buffer problem inside the PC which was a source of desynchronization of the events between the boards
First results look promising
Preliminary map has been produced
Bench still has to be optimized
Is a gain 10 sufficient ?