1. Christophe Beigbeder/ PID meeting
Analog board status and considerations on the electronics design
SCATS status
Tentative summary of the discussions on the acquisition system for the test setup and the CRT
Conclusion
Christophe Beigbeder/ PID meeting
September 13th 2011

2. Christophe Beigbeder/ PID meeting
Board developments
Mezzanine : 8 channels ( analog part )
Mother board : ADC + SCATS + FPGA
- Associates time & charge
- Data packing.
- Bus interface : USB, Aurora (?)
-> equips both PM test Orsay and CRT
Christophe Beigbeder/ PID meeting
September 13th 2011

3. Christophe Beigbeder/ PID meeting
Mezzanine
- The first prototype will permit testing three different designs.
Christophe Beigbeder/ PID meeting
September 13th 2011

4. Mezzanine : Implementation
Mother board
Christophe Beigbeder/ PID meeting
September 13th 2011

5. Christophe Beigbeder/ PID meeting
Layout
External power supply
(Stand alone mode)
6 Layers. Components on both sides
Spare links
Christophe Beigbeder/ PID meeting
September 13th 2011

6. Christophe Beigbeder/ PID meeting
Mother board
Designed to be used for different purposes:
Testing the SCATS
Equipping the CRT
Use in different test setup.
Easy integration in Gary’s acquisition system ( next slide and discussion )
USB readout for standalone test
Due to the relatively low count rate per channel, we put one ADC per 4 channels
Design start soon. 6 months to get it on the table.
Christophe Beigbeder/ PID meeting
September 13th 2011

7. Design considerations
Fast ADC are for most of them synchronous to a clock
ADC with S/H command have a limited bandwidth.
S/H amplifiers are relatively slow for the analog part ( ~ MHz) or extremely expensive ( GHz bandwidth ).
We will use discrete S/H. The ballistic deficit will have to be evaluated. We will not be able to match the expected performances of the PIF.
PIF will be designed in 2012
The charge/time matching makes the synchronization very difficult if separate readouts. We plan to have the PIF inside SCATS after having validated the design.
The charge and time will follow their path the same way inside the chip.
The two will be associated inside the chip and read together.
Christophe Beigbeder/ PID meeting
September 13th 2011

8. Design considerations
Implementation of the shared charge measurement gives heavy constraints on the design:
The neighbors have to be limited : Inside a row of 8 channels .
The systematic readout of the 2 neighbors has a impact on :
The size of the event and the occupancy.
The dead time per channel.
We have to evaluate the impact on the electronics performance and number of ADC.
Christophe Beigbeder/ PID meeting
September 13th 2011

9. Christophe Beigbeder/ PID meeting
SCATS
Full custom FIFOs post layout simulation results
Digital part : synopsis & layout
Digital part : post synthesis simulation results
Christophe Beigbeder/ PID meeting
September 13th 2011

10. Christophe Beigbeder/ PID meeting
SCATS Fifo Timings
Summary of the measurements (typical) which have been performed on the following signals:
wr<0>, rd<0>, in_fifo<0>, out_fifo<0>
Min pulse width for writing in CH0 = 500 ps
Min pulse width for reading from CH0 = 1 ns
Hold time min = 0 ns
Setup time min= 0 ns
tRS0 = 2.32 ns
tRS1 = 2.4 ns
Settling time on read “0” in fifo input Settling time on read “1” in fifo input
Christophe Beigbeder/ PID meeting
September 13th 2011 10

11. Christophe Beigbeder/ PID meeting
Digital design made with the following softwares:
Global synthesis
RTL Compiler 9.1
RTL-to-GDSII System, Place & Route Tool
SOC Encounter 8.1
Digital simulations
NC-Verilog 8.2
Extraction : DIVA – ASSURA
Simulation “ AMS 11
Christophe Beigbeder/ PID meeting
September 13th 2011

12. Christophe Beigbeder/ PID meeting
The final layout of the digital part of SCATS is very close to the diagram below
PCSM
Afifo_ctrl
MUX_OUT
ch0
16 ch
PCSM
Afifo_ctrl
ch15
Ecs_scats
GSM
16 ch
16 ch 12
Christophe Beigbeder/ PID meeting
September 13th 2011

13. Christophe Beigbeder/ PID meeting
Power stripes width are larger than in the previous version
Following modules must not exceed a height of 65µm to meet design area constraints
Asic_fifo_control : 612.6µmx 65µm
Pcsm : µm x 65µm 13
Christophe Beigbeder/ PID meeting
September 13th 2011

14. Christophe Beigbeder/ PID meeting
Mux_out : 252.6µm x 1252µm
Gsm : µm x 236.2µm
Ecs :1082.6µm x 260µm
Christophe Beigbeder/ PID meeting
September 13th 2011

15. Christophe Beigbeder/ PID meeting
Scats : 4950µm*4726µm = 23.4 mm2 15
Christophe Beigbeder/ PID meeting
September 13th 2011

16. SCATS digital part simulations
Simulation post layout of all previous digital components instantiated in one test bench
The results below are the mean value of all channels
 Clk=100MHz Hit_freq= 10 MHz
evt_size=0 rate=61 words in fifo=7
evt_size=1 rate=33 words in fifo=7
evt_size=2 rate=22 words in fifo=7
evt_size=3 rate=16 words in fifo=7
Clk=100MHz Hit_freq= 20 MHz
evt_size=0 rate=34 words in fifo=7
evt_size=1 rate=21 words in fifo=7
evt_size=2 rate=11.5 words in fifo=7
evt_size=3 rate=18 words in fifo=7
M. EL BERNI – LAL – 09/2011 16
Christophe Beigbeder/ PID meeting
September 13th 2011

17. Christophe Beigbeder/ PID meeting
Simulation post layout of all previous digital components instantiated in one test bench
The results below are the average of all CH
  Clk = 100MHz Hit_freq = 1 MHz on all CH except for CH14  Hit_freq = 20 MHz
evt_size=0 rate=97 word=1
evt_size=1 rate=97 word=2
evt_size=2 rate=96 word=4
evt_size=3 rate=96 word=6
The results below are for CH14 only
  Clk=100MHz CH14  Hit_freq=20 MHz
evt_size=0 rate=64 word=2
evt_size=1 rate=64 word=4
evt_size=2 rate=52 word=6
evt_size=3 rate=36 word=7
Christophe Beigbeder/ PID meeting
September 13th 2011

18. Christophe Beigbeder/ PID meeting
Why we didn't submit
SCATS was almost ready to be submitted last week. But top level simulations (complete chips – post layout) displayed a mismatch between old software and new one.
We want to make many post layout simulations and we need to perfectly understand the new IC tools which can perform such heavy ones.
SCATS is powerful but its drawback is it is a “ black box “ There is no way to see anything and to understand something if there is no data coming out.
We had a major computer failure during end of august we were not able to work on the chip.
The chip costs 15k€: we want to be 100% confident before submitting it.
The mother board cannot be ready before 5 months from now and it was not useful to get the chip before it
=> for all these reasons we decide to postpone the submission to November
Christophe Beigbeder/ PID meeting
September 13th 2011

19. Tentative summary of the discussions on the data acquisition
Gary’s acquisition system
Aurora protocol
Fiber
Service box
Service box
ADC
FPGA
XILINX
ADC
SPECS
SPECS
slave
slave
ADC
Compact PCI crate
MXI Express link ?
Christophe Beigbeder/ PID meeting
September 13th 2011

20. Christophe Beigbeder/ PID meeting
Acquisition system : 3 versions using the Compact PCI
Version1 :
Price : (crate, board, PC,)
Time of implementation, specific firmware development
(see Shih-Min Liu; Alan Teng; C.H. Wang NUU, Taiwan presentation)
Limited software development.
Version 2 :
Price : (crate, board, PC, Transceiver)
XILINX FPGA knowledge.
Version 3 :
Price (IP, crate, board, PC, )
2 firmware development .
Module
Service box
Service box
ADC
Vers 1
FPGA
ALTERA
ADC
SPECS
SPECS
slave
slave
ADC
Aurora protocol
Fiber
Module
Service box
Service box
ADC
Vers 2
FPGA
XILINX
ADC
SPECS
SPECS
slave
slave
ADC
Aurora protocol
Fiber
Compact PCI crate
MXI Express link ?
Module
Service box
Service box
ADC
FPGA
ALTERA
ADC
Fiber Chanel protocol
FIber
SPECS
SPECS
slave
slave
ADC
Christophe Beigbeder/ PID meeting
September 13th 2011

21. Christophe Beigbeder/ PID meeting
CRT acquisition system version 4
Price : A2818 CAEN board
Specific firmware development (comet protocol).
PC acquisition software development.
Service box
Service box
ADC
FPGA
ALTERA
ADC
SPECS
SPECS
slave
slave
ADC
Conet 1 or 2 protocol
A2818 CAEN board
MXI Express board
MXI Express link ?
Compact PCI crate
Christophe Beigbeder/ PID meeting
September 13th 2011

22. Christophe Beigbeder/ PID meeting
CRT acquisition system version 5
Most popular protocol.
Firmware development on going at LAL.
Service box
Service box
ADC
Ehernet Protocol
FPGA
ALTERA
ADC
SPECS
SPECS
slave
slave
ADC
Compact PCI crate
MXI Express link ?
MXI Express board
Questions : Is the compact PCI only used to push data into the PC ? If yes, cannot we bypass it and use a cheaper solution than compact PCI ?
How do we plan to debug our lab without having PCI and Gary’s boards ?
Do we need to have Gary’s electronics everywhere even when DAQ is not needed ?
Christophe Beigbeder/ PID meeting
September 13th 2011

23. Christophe Beigbeder/ PID meeting
Conclusion
LAL H8500 test setup is ready for being tested
The design of the mezzanine board is finished.
S/H still to be implemented.
Charge sharing architecture has to be discussed and clarified
Mother board : design starting soon
SCATS : layout of the 16-channel chip finished.
post synthesis simulation ok.
post layout simulation on the complete chip are ongoing to fully understand the chip with the new IC tool.
Submission in November
We need to go ahead on the study of backplane, cooling, power supplies, cables to get ready for the TDR .
Christophe Beigbeder/ PID meeting
September 13th 2011