1. Electronics for FTOF prototype: status of the 16-ch WaveCatcher board D.Breton & J.Maalmi (LAL Orsay)
2011
2010 …

2. The board 1.6mm thick 10 layers 233 x 220 mm² 3200 components
25 power supplies (5 global, 20 local)
4 4-channel blocks (used as mezzanine on other boards)
2 channels dedicated to digital signals

3. Block diagram of the 16-channel WaveCatcher
- This board is compatible with both SAM (256 cells/ch) and SAMLONG (1024 cells/ch) ASICs
(circular analog memories)
- SAMLONG: baseline.
- The board can be connected to a backplane => possibility to scale the system up to 320 channels in a crate
SAMLONG Chip 1024 pts GS/s 2 Channels
Dual 12 bits
ADC
4 Analog Input
Trigger In/out
FPGA
6U x 220mm Format
USB 480 Mbits/s
Optical fiber connector

4. 2-channel front-end diagram
Low Threshold + -
High Threshold
SAMLONG
(1024 sampling cells)
Ch0
FPGA
Controller
½ Front End
(TimeStamp,Q,A)
Trigger out
BACKPLANE
12-bit
ADC
High Threshold
Ch1
Trigger in
Run, read
clk
Event data
x 8
USB

5. LP-BUS: for a tree architecture
FT2232H or ….
USB/Ethernet
Interface
Needed if not interfaced with a FT2232H…
LP-out 0
LP-in
FPGA
Interface block
LP-out 1
LP-out N
Reg
Fifo
RAM
internal registers, Fifos, RAMs …
Layer 1
Arbitrer
LP-Bus 0
LP-Bus 1
LP-Bus N
LP-out 0
LP-in
FPGA
LP-out 1
LP-out M
Reg
Fifo
RAM
FPGA
LP-in
Reg
Fifo
RAM
FPGA
LP-in
Reg
Fifo
RAM
Layer 2
Arbitrer
Arbitrer
Arbitrer
LP-out 0
LP-out 1
LP-out M
LP-out 0
LP-out 1
LP-out M
LP-out 0
LP-in
FPGA
LP-out 1
LP-out P
Reg
Fifo
RAM
LP-out 0
LP-in
FPGA
LP-out 1
LP-out P
Reg
Fifo
RAM
LP-out 0
LP-in
FPGA
LP-out 1
LP-out P
Reg
Fifo
RAM
LP-out 0
LP-in
FPGA
LP-out 1
LP-out P
Reg
Fifo
RAM
Layer 3
etc …

6. LP-BUS : based on synchronous mode of FT2232H
FPGA
L(n)
Data [7:0]
FPGA
L (n+1) L P - O U T B C K L P - I N B O C K
RXF
TXE WR RD
n_OE (sync mode)
CLK (sync mode)
Ecriture
Lecture

7. Principle of« russian dolls »
Mutli-layer protocol based on encapsulation and decapsulation of the data field with an evolution of the « LAL-USB » protocol
Example of a N-byte write frame towards Layer 3.
Byte/Bit B7 B6 B5 B4 B3 B2 B1 B0
Header 1
Ctrl1
(N -1+ (n-1)*5)(LSB)
Ctrl2
(N - 1+2*5)(MSB)
Ctrl3
R/W =0
local = 1
BC*=0/1
SubAddress1
(N )(LSB)
(N )(MSB)
R/W =1
SubAddress2
N - 1(LSB)
N - 1(MSB)
local = 0
SubAddress3
Data
Payload Data* (N Bytes to be written)
Trailer
Protocol is adapted to tree architectures: same firmware blocks at all layers + possibility for broadcast access

8. Present and future board features (not exhaustive)
Possibility to add an individual DC offset on each signal
Possibility to chain channels by groups of 2
2 individual trigger discriminators on each channel
External and internal trigger + numerous modes of triggering on coïncidence (11 possibilities including two pulses on the same channel => useful for afterpulse studies
Embedded digital CFD for time measurement
Embedded signal amplitude extraction
Embedded charge mode (integration starts on threshold or at a fixed location) => high rates (~ 3.5 kEvents/s)
2 extra memory channels for digital signals
One pulse generator on each input
External clock input for multi-board applications
Embedded USB and Serial Lite/Fibre Channel/Conet interfaces
Possibility to program the FPGAs via USB/Backplane/Altera Blaster

9. Front-end block has been integrated in a mezzanine
The latter has been mounted on a CAEN USB-driven motherboard
Almost fully validated!
First characterization results are available: noise level : 0.72 mV, signal bandwidth ~ 500 MHz (equivalent to single WaveCatcher board)
This mezzanine permitted an anticipated hardware debug and predesign of firmware for the 16-channel board (should be sold by CAEN soon).

10. Acquisition Software: up to 16 ch  soon 64 ch!

11. Measurement panel

12. Preliminary results - 1
We send pulses from a pulse generator (1V pp, rise & fall time: 1.6 ns, FWHM 2 ns)
We vary the distance.
Time jitter between two channels on the same SAMLONG chip:
Δt ~ 0 ns (Ch1 – Ch0) jitter = 4.2 ps rms
Δt ~ 10 ns (Ch1 – Ch0) jitter = 7.0 ps rms

13. Preliminary results - 2
We send pulses from a pulse generator (1V pp, rise & fall time: 1.6 ns, FWHM 2 ns)
We vary the distance.
Time jitter between two channels on DIFFERENT SAMLONG chip:
Δt ~ 0 ns (Ch1 – Ch0) jitter = 8.3 ps rms
Δt ~ 10 ns (Ch1 – Ch0) jitter = 9.6 ps rms

14. Wavecat_16ch in common trigger mode
Front-end block
Soft_trig
Controller
Ext_trig
sel_edge_ch0
From all
daughterboards
discri
Short
pulse
Rate
counter
ch0_input +
trig_thresh0 _
ch0_trig_mask
Gate
Comb
trigout
SAM_clk
length[6..0]
or/and
sel_edge_ch1
discri
Short
pulse
1ch/2ch
ch1_input
or/and +
trig_thresh1 _
Rate
counter
ch1_trig_mask
Gate
Masked AND
SAM_clk
length[6..0]
From other 2-ch block
trigout[2]
en_trig
Pretrig
Time
Counter
To all
front-end blocks
Posttrig
trigin
stop
SAM
recording SM
SAM
Readout SM LP
Arbitrator
evt_rdy
From other
front-end blocks
start LP
Arbitrator wr
last_byte
rd_req wr rd
LP_OUT interface
rd_req
Event
Buffer
FIFO (4k)
n_wr
ch0_input
LP_IN
interface
rd_req
SAMLONG
ADC
data
LP_Bus
Read
FIFO (32)
sel
LP_IN
interface
USB
ch1_input
n_rd
n_rd
n_wait
n_empty
n_wait
Event
Buffer
FIFO (4k)
Write
FIFO (32)
User_Bus
From other 2-ch block
n_wr
User
EEPROM
User
registers
User
EEPROM
User
registers

15. Building large scale systems
Controller
board
Clock & common trigger
Individual triggers
Up to 10
WaveCatcher boards
Up to 10
Crate backplane interconnections
DAQ connected
to all boards or only
to controller
USB/
Ethernet
To synchronise N boards a controller board is needed + backplane for the interconnections
we are building a very compact 64-channel system :
 can be used for the FTOF sector prototype with fourteen 4-channel MCP-PMTs (SL10)
we are also building a 320-channel system in 6U-crate (SuperNemo experiment).

16. SAMPIC: the ps TDC for FTOF
Critical path
for time
measurement
We started designing the SAMPIC ps TDC a few months ago
=> This ASIC makes use of the new AMS 0.18 µm CMOS technology
First version will house 8 blocks of 64 analog memory cells
Sampling is performed between 2 and 10 GS/s
Signal bandwidth is ~ 1 GHz
Digitization will be performed inside the chip with a parallel Wilkinson ADC running at 2 GHz in each cell
The 2-GHz clock is not distributed to the cells but runs a unique gray counter
The cells house a fast comparator and a latch
Submission is targetted for next month
I have to rapidly design the test board (with ps level performance !)
First tests should take place in July

17. Conclusion
First results of the new 16-channel WaveCatcher board look very promizing: time precision is well below 10ps rms
even between different chips
We are now finalizing the firmware and the software will follow very soon
=> huge task especially since Jihane just left for her second baby … (foreseen April 13th)
We have designed a compact 64-channel
system
25 cm x 10 cm x 30 cm with embedded power supply
Single link to the PC (USB and Ethernet)
Available very soon (but software has to be extended …)
Up to 320 channels can be housed in a 6U crate
Such a system is currently also being developped.
The SAMPIC TDC prototype will soon be available
=> This ps « analog » TDC is a major challenge …