SR Flip-Flop Negative Edge Triggered Flip-Flops The SR Flip-Flop How it works Where does it fit with others Master-Slave Flip-Flops Negative Edge Triggered Flip-Flops

The SR Flip-Flop S R Action 0 0 Keep state 0 1 Q = 0 1 0 Q = 1 1 1 Undefined Q Q R

Clocked SR Flip-Flop S Q CLK Q R

Clocked D Flip-Flop D CLK Q Q

JK Flip-Flop J Q CLK Q K

T Flip-Flop T CLK Q Q

Master-Slave Flip-Flop J Q CLK Q K

Master-Slave Flip-Flop Happens only once per clock cycle Acts as a double check

Negative Edge Triggered D Flip-Flop Q CLK Q D

Negative Edge Triggered D Flip-Flop Same benefits as a Master-Slave More efficient

Finite State Machines What they are Build One

What it is A way of modelling using “states” States Transitions Actions

Example From Book (Pg. 464)‏ Modulo-4 Synchronous Counter 00 to 11 and repeats Has one input to reset the counter and start over R S1S0 T+1 T+1 0 0 0 01 01 0 0 1 10 10 0 1 0 11 11 0 1 1 00 00 1 0 0 00 00 1 0 1 00 00 1 1 0 00 00 1 1 1 00 00

How Do We Build This? Facts Start with two D Flip-Flops Two Bites of storage One input Two output Start with two D Flip-Flops Four states so four ANDs Two outputs so two ORs Plug it all together and fill in the gaps

The Build (Pg. 467)‏ RESET D Q q1 CLK Q D Q q0 Q