Prof. Jang-Ung Park (박장웅) Chapter 1. Overall Process of Integrated Circuits Prof. Jang-Ung Park (박장웅) http://wearable.unist.ac.kr

Overall Process of Integrated Circuits Ingots and Wafers : The current electronics are based on Si semiconducting material. : Single crystal Si is grown from the melt (of sand, SiO2), using Czochraski technique. melting temperature of Si: 1414 oC [ Si ingot ] : The crystal growth rate is about 10 m/s. : The ingot is cut into thin slices of wafers (thickness: about 100~500 m). : The wafers are etch polished on one or both surfaces for the mirror-like smooth roughness.  Can we produce Si wafers with very large diameters over 1 m?

Overall Process of Integrated Circuits Si Wafer {1 1 0} direction : Single crystal Si wafers have the flat notch to indicate {1 1 0} crystalline direction.

Overall Process of Integrated Circuits Thermal Oxidation of Si : Native SiO2 layers are naturally grown in air (room temperature) on surfaces of bare Si wafers. Si wafer (thickness: 100-500 m) native SiO2 (thickness < ~4 nm) : Thick SiO2 layers with controlled thicknesses (about 50 nm~900 nm) are further grown by placing the wafers in a furnace at temperatures of 900 to 1100 oC in an oxidizing ambient, generally dry oxygen or water vapor. Si wafer (thickness: 100-500 m) SiO2 (thickness : about 50-900 nm) Si wafer furnace : oxidation of selective areas  How can we make patterns of the nitride mask made?

Overall Process of Integrated Circuits Photolithography and patterning : metal lines or dielectric patterns can be produced on sample using a photo-sensitive polymer (photoresist). [ etch-back process ] Deposition of a metal / dielectric layer on a sample Coating a photoresist (PR) layer UV exposure through a glass photomask Dissolving the UV-exposed areas of PR Etching the underlying metal or dielectric layer Removing PR The metal or dielectric layer is patterned with geometries same to the mask patterns.

Overall Process of Integrated Circuits Photolithography and patterning Coating a photoresist (PR) layer on a sample [ lift-off process ] UV exposure through a glass photomask Dissolving the UV-exposed areas of PR Depositing metal or dielectric layer on the PR Removing PR (metal areas on PR are peeled off together.) The metal or dielectric layer is patterned. : The pattern image from the lift-off is inverse to etch-back process.

Overall Process of Integrated Circuits Glass Photomask incident light (UV) Cr patterns (thickness: ~100 nm) Quartz Glass (thickness: about 0.5 ~ 1 mm) Photoresist substrate Photoresist patterns [ after developing (positive photoresist) ] metal substrate [ after etch-back process ] substrate Positive photoresist: the light-exposed areas are removed after developing. Negative photoresist: unexposed areas are removed after developing. substrate [ after lift-off process ]

Overall Process of Integrated Circuits Doping of Si : Extra carriers such as electrons and holes are generated by inserting dopant atoms (B, As) into Si lattice.  Electric conductivity of Si significantly increases by the doping process. [ doping using ion-implantation ]

Overall Process of Integrated Circuits [ cross-sectional image of a single transistor ] Metallization : In integrated circuits, one usually connects various devices with metal lines in order to carry out current or transport electrons / holes. : Interconnects are these metal lines, and patterned by photolithography.

Transistor Size (Moore’s Law) : The number of transistors on integrated circuits doubles approximately every two years. : Gordon E. Moore (Intel co-founder) predicted this trend in 1965. : Transistors were made smaller through advances in photolithography, but this size reduction will be limited soon. - minimum feature size is already below 45 nm in 2010 by using excimer laser lithography (: 248 and 193nm). : The cost of building chip fabrication plants will continue to increase, and the return on investment to decrease until it becomes fiscally untenable to build new plants (Moore’s Second Law).

Marketshare Position of Macro-electronics Macro-electronics: Large-area electronics 1950 1960 1970 1980 1990 2000 2010 Year 250 200 150 100 50 $US Billions Semiconductor shipments Flat-panel Display shipments

Intrinsic Mobilities &Eg of Various Semiconductors Source: Intel

High-Field Effects (hot carrier effects) In Ohm’s law, vd: average drift velocity m*: effective mass of e- : relaxation time E: electric field strength vr: ~ 106 m/s vd ~ thermal velocity (vth) vth: ~ 105 m/s (due to the lattice scattering) high-field effect (Ohm’s law is not valid) : used to maximize vd (device speed) Movie (the temperature of the current CPU processors > 350oC)

Approach to Increase Mobility of Si Strained Si (IBM, 2001 June) : Chip speeds (including mobilities) can be enhanced up to 35% faster.

Misleading Conventional Thoughts about Si 1. Si wafers are expensive: not correct Si wafer : ~20,000 won/wafer (15 won/gram) Ex) One of the popular organic semiconductors, pentacene (unpurified): ~106 won/gram 2. Large-area processing is impossible: not correct Current Gen8 LCD displays use Si TFTs (size: about 2m  2m). 3. Si is not flexible but fragile: not correct  All materials, even diamonds, can be flexible!  Flexibility is not a material’s issue, but design’s issue. 4. Si is not stretchable: not correct (design issue) wavy Si PDMS