Nonvolatile memories: L14 04262017 ECE 4211 UConn F. Jain Chapter 13A CMOS Imaging (pp. 743-746). Chapter 13B Charge Coupled Devices (CCDs) pp. 747 Nonvolatile memories:

CMOS Imaging (pp. 743-746). Architecture is shown in Fig. 1. Fig. 1a shows an array of pixels, row select logic (which selects one row at a time) using a decoder, column select logic (which connect the selected row to analog signal processors (ASPs), analog-to-digital converters (ADC), and a timing and control logic block. Fig. 1b shows detailed diagram interfacing timing and control with row and column decoders. The analog signal processors (ASPs) provide charge integration, gain, sample and hold, correlated double sampling, and fixed pattern noise (FPN) suppression. The pixel charge, proportional to intensity of light, is converted into digital output by the analog-to-digital converters (ADCs) located in each column.

Passive and Active pixel addressing IMAGE READOUT MODES: Progressive scanning is generally used. The speed of scanning is increased by skip readout mode where alternate or every third pixel is readout. Window readout mode is used when a selected region of pixels is scanned. Pixel Circuits: Pixels comprise a photosensitive device, an access FET, and processing electronics. There are two types of photosensitive devices, which converts light into current or voltage levels. These include a photodiode and a photogate FET which has poly-Si gate that permits photons to be incident and get absorbed.   Passive Pixel: Photodiode based passive pixel is shown in Fig.2. Fig. 2 shows passive pixel consisting of a photodiode and an access FET. When a row is selected and access FET is turned on, the photodiode is connected to a vertical column bus. A charge Integrating Amplifier (CIA) circuit reads out, and keeps the column bus voltage at a desired level. The photodiode voltage is reset to the column voltage. The charge on the photodiode is connected by CIA into a voltage which is proportional to the photosignal based charge depleted on to the photodiode. Passive Pixel: Photodiode based passive pixel is shown in Fig.2. Fig. 3 Photodiode Based Active Pixel Sensor Circuit. Fig. 4 Photogate type active pixel.

Photodiode based active pixel: Fig. 3 shows photodiode based active pixel. The controller via RST signal resets the photodiode potential to VRST. Photons (above band gap of Si) are absorbed by creating electron-hole pairs, reducing the potential across the photodiode. The pixel is read out by row/column select when FET Msel is accessed by Row Select. Here, FET MSF (Source-Follower) buffers the photodiode. Photogate type active pixel.   : Fig. 4 shows a photogate based active pixel. This scheme integrates x-y readout and CCD type MOS Photogate (PG). The charge generated by photons under the photogate is transferred when FET labeled as TX is enabled by row select RS, and connects it to a column bus. Photogate and TX share a bridging diffusion providing electrical connectivity. The other end of FET TX is connected to FET MRST which resets the voltage at the drain end of TX FET. There are 5 transistors per pixel. Photogate based active uses poly Si gate to permit photons to be absorbed in Si substrate (for PG FET).

Charge Coupled Devices (CCDs) pp. 747

Figure1a,1b,1c. MOS capacitors as CCD illustrating the sequence of voltages needed to obtain charge transfer from one capacitor to the other. P.749

Charge generation and charge transfer in CCDs P.750

Charge detection in CCDs P.750

Imaging in CCDs

Nonvolatile Floating gate memories: Ch. 11 State of the art vertically stacked NVM cells

Fig. 11(c-3). Erase operation voltages in a NOR cell. Nonvolatile Memory: NOR architecture: READ and Write Fig. 11(c-3). Erase operation voltages in a NOR cell.

Nonvolatile Memory: NAND

VT or VTH equation Al-SiO2-pSi Al-SiO2-nSi

DVTH Dopant density variation (due to implant or in substrrate) Oxide or gate insulator thickness variation Oxide dielectric constant variation in thin films of 1-2nm Channel width and length variation, Oxide charge density variation