EUDET France – 05/04/07 – Rémi CORNAT (LPC) 1 CALICE instrumental chain looking (not so) forward to EUDET Overview Wafer characterization Sensor test In situ debug and maintenance DAQ LPC LAL LLR

EUDET France – 05/04/07 – Rémi CORNAT (LPC) 2 CALICE instrumental chain History Seoul dec. 06 LLR 9 jan. 07 LLR 24 jan. 07 LAL 9 fev. 07 LLR 13 fev. 07 LLR 20 mar. 07 CERN 23 mar. 07 ANR proposal involves LPC, LLR & LAL Jean Claude Brient Jean-Charles Vanel Akli Karar Marc Anduze Julien Fleury Pascal Gay Francois Morissau Rémi Cornat … Sorry for those forgotten

EUDET France – 05/04/07 – Rémi CORNAT (LPC) 3 ECAL Instrumental chain overview from Wafer to data acquisition Detector VFE Read-out DAQ Test bench Wafer Crosstalk studies Design validation ASUDAQ Sensor validation Cosmic tests ISDDAQ Debug, Monitoring Maintainance Analysis Software SW reconstruction Towards EUDET, Validation & Test of the whole chain R&D test tools for sensor and electronics on beam behavior monitoring SKiROC Wafer ASU

EUDET France – 05/04/07 – Rémi CORNAT (LPC) 4 Wafer Unexpected behavior seen during test beam : SQUARE events ! Unmatched pattern according to physics models… Has to be understood and solved

EUDET France – 05/04/07 – Rémi CORNAT (LPC) 5 Wafer Understand Square events origins Crosstalk studies according to design options Effects of a particle hit on guard ring could be propagated to every bordering pixels Try to reproduce the phemenon Test new designs layout technologic improvements As result, select the best design technique…

EUDET France – 05/04/07 – Rémi CORNAT (LPC) 6 Wafer Setup and tools Simulation capacitive coupling guard ring layout PCB for test electronics Test bench pulse generator micropositioner & probes shaper + scope Characterization Charge injection pixel signal analysis Wafer XYZ table Needles accessible area Supporting PCB I(V) / C(V) ? CAD verified OPEN QUESTION

EUDET France – 05/04/07 – Rémi CORNAT (LPC) 7 Wafer short term actions Simulation –Software know-how & test case (first try on 10th of april) –Need to know what to simulate Mechanical compatibility test –Probe system vs wafer dimensions PCB design –Connector –Charge injector –Shaper Interaction with manufacturer –Layout options –Common wafer floorplan CAD verified OK Proposal J-C. V. OPEN QUESTION

EUDET France – 05/04/07 – Rémi CORNAT (LPC) 8 ASUDAQ Cosmic test of ASU ASUDAQ PC USB Active Sensor Unit Features full slow control including internal probing system control access to analog test points (embedded ADC) read out of 4 SKiROC through USB & PC cosmic bench environment support (triggers) mechanical jaw providing damageless contacts to ASU Cosmic test bench for ASU characterization. First R&D step towards EUDET production tests

EUDET France – 05/04/07 – Rémi CORNAT (LPC) 9 ASUDAQ first attempt of an architecture USB PC slow control ADC data probe Read out interface jaw TRIG Simple design based on FPGA USB interface for PC ADC for VFE internal probing system needs probe signal on ASU connector Trigger and timing signals for cosmic test bench read-out Mechanical interface ? Connectors for 1-4 ASU can be foreseen Software tasks to be specified OPEN QUESTION

EUDET France – 05/04/07 – Rémi CORNAT (LPC) 10 ASUDAQ short term actions Collect informations –ASU I/O connector specs –VFE documentation Understand current design First HDL simulation –Reuse of existing code (SKiROC & HaRDROC) Define cosmic test bench

EUDET France – 05/04/07 – Rémi CORNAT (LPC) 11 USB issue USB is in use at LPC since Q1’04 featuring FTDI245BM chip Prototyping board exists for very first developments (FPGA based) Heavily used on –L0 trigger decision unit of LHCb –Spare slow control of LHCb preshower front end board –ADC test bench at LPC Will further evolve to version 2 (student project since 2004) for both firmware and software USB LVDS I/O VME / TTL I/O SPARE Data throughput limits of FTDI 150 ns cyle time and 2kB FIFO  6 MB during 400 µs  slow software (?)

EUDET France – 05/04/07 – Rémi CORNAT (LPC) 12 InSituDebugDAQ concept Standard DAQ Special link DebugDAQ Dedicated PC On beam simplified DAQ devoted to monitor and debug a few SLABs chip radiation tolerance accurate diagnostic of unexpected behavior monitoring (internal probes) maintenance Can run alone, eventually with no beam compatible with machine interface or specific trigger and timing Dedicated Software aimed to ease debugging Needs DIF (already glued to SLAB) Machine Interface Or Stand alone CCC Simultaneous DAQ operations allowed

EUDET France – 05/04/07 – Rémi CORNAT (LPC) 13 InSituDebugDAQ architecture options ISSD as an interface between DIF and a PC by replacing the standard DAQ system ISSD as an interface between DIF and a PC in parallel to DAQ ISSD connected to the standard concentrator (LDA) But no access to VFE internal probing (analogue) Bypass standard CCC if needed Additional connector and firmware upgrades Flexibility and cabling X

EUDET France – 05/04/07 – Rémi CORNAT (LPC) 14 DAQ vs DIF (idea) TRIG DIF is a light ASUDAQ, ASUDAQ is a DIF with extended features slow control of internal probes ADC for probe output (might be integrated into VFE ?) probe data read-out (additional or separate flow) dedicated software modules ISDDAQ is a DIF with extended features and direct read-out Hard/firm/software developments for ASUDAQ & ISDDAQ are Very similar as for DIF CCC additionnal signals for users defined trigger (cosmic, no beam, …) Alternative Slow control access Mechanical interface to ASU (ASUDAQ)  (e)xtendedDIF concept ASU ISD

EUDET France – 05/04/07 – Rémi CORNAT (LPC) 15 eDIF proposal first attempt architecture eDIF is a DIF including optional ASUDAQ features Unwanted components may not be soldered USB may be deported using the test connector foreseen on DIF or on LDA Additional CCC signal through debug con. The event builder add probe data into data flow as coming from ghost SkiROC (combined data flow mode) Provides two slow control access Basic DAQ through USB (ASUDAQ) Fully compliant with LDA (DebugDAQ) Transparent mode (standard DAQ) LDA interface USB PC slow control ADC data probe Event builder CCC

EUDET France – 05/04/07 – Rémi CORNAT (LPC) 16 InSituDebugDAQ architecture proposal eDIF LDA SLAB ODR TRIG ISDDAQ PC Then it needs (e)xtended LDA… (CCC multiplexing) or custom interface board (serial LVDS to NI DAQ) Carte DAQ NI PCI-7811R ? FPGA based, 160 I/O to PCI buffer flush mode (continuous streaming to PC) ? Direct connection to LDA would avoid risky cabling operations and highest flexibility eDIF is needed for VFE probes and mixed data flow mode (probe+DAQ) Software tools Light LDA for early devlopments OPEN QUESTION

EUDET France – 05/04/07 – Rémi CORNAT (LPC) 17 load_ecs 1 bit error correction 2 bits error detection 30 bits word (for ex.) –24 data bits (2x12) –5 redundancy bits –1 global parity bit On the flow Encoding/decoding (DAQ) Shared among slow control registers Heavily used –Final design of LHCb preshower –CMOS chip HDL ready Hamming coding secure data transfer OPEN QUESTION

EUDET France – 05/04/07 – Rémi CORNAT (LPC) 18 Conclusion ASUDAQ and ISDDAQ need analogue signals of internal probing system to be connected to DIF eDIF concept architecture choice Combined data flow mode Additional features to today SLAB and DAQ Wafer test bench being set up PCB specifications Keithley choice Shaper SILVACO simulation tools Hamming coding of data could secure data transfer and configuration data ASUDAQ first developments on prototyping board ASU connector issue ISDDAQ architecture issue Internal probes Simultaneous DAQ Flexibility Actions on the whole chain to make EUDET a success R&D on wafer Validation, debugging and maintenance tools

EUDET France – 05/04/07 – Rémi CORNAT (LPC) 19 MAIA BEE (Y) M aintenance A pparatus I ncluding (data) A cquisition (on) B eam (for) E UDET E CAL Private joke

EUDET France – 05/04/07 – Rémi CORNAT (LPC) 20 CALICE instrumental chain looking (not so) forward to EUDET Overview Wafer characterization Sensor test In situ debug and maintenance DAQ ILC LPC Clermont-Ferrand