Front End Electronics for SOI Monolithic Pixel Sensor 1/25 Front End Electronics for SOI Monolithic Pixel Sensor T. Miyoshi, Y. Arai, Y. Fujita, K. Hara1, S. Honda1, Y. Ikegami, Y. Ikemoto, I. Kurachi, S. Mitsui, A. Takeda2, K. Tauchi, T. Tsuboyama, M. Yamada High Energy Accelerator Research Organization (KEK) 1Univ. of Tsukuba 2Kyoto University 23/9/2014 (Tuesday) 11:35 - 12:00 ASICs v.3

MPW FY13-1 Outlines Introduction Progress of SOI sensors Sensor layout 2/25 Outlines Introduction Progress of SOI sensors Sensor layout Pixel layout and circuit Current issues and solutions Future plan and summary MPW FY13-1

SOI Wafer for monolithic sensor 3/25 SOI Wafer for monolithic sensor Smart cutTM by Soitec Splitting Oxidation Cleaning and bonding Implantation Low R High R circuit Initial silicon sensor SOI wafer High Resistivity Silicon: Two choices N-type Czochralski, NCZ, 700 Ohm-cm, 300 mm-thick N-type Float Zone, NFZ, 2-7k Ohm-cm, 500 mm-thick

The features of SOI monolithic pixel sensor 4/25 SOI Monolithic pixel sensor Insulator (SiO2) Low R Si Targets High-Energy Physics X-ray astronomy Material science Non-Destructive inspection Medical application High R Si The features of SOI monolithic pixel sensor No mechanical bump bonding. Fabricated with semiconductor process only Fully depleted (thick & thin) sensing region with low sense node capacitance (~10 fF@17 mm pixel)  high sensor gain ・SOI-CMOS; Analog and digital circuit can be closer  smaller pixel size Wide temperature range (1-570K) Low single event cross section Technology based on industry standards; cost benefit

Process Summary KEK organizes MPW runs twice a year 5/25 Process Summary 25mm x 30mm KEK organizes MPW runs twice a year Mask is shared to reduce cost of a design Including pixel detector chip and SOI-CMOS circuit chip Process (Lapis Semiconductor Co. Ltd.) 0.2mm Low-Leakage Fully-Depleted (FD) SOI CMOS 1 Poly, 5 Metal layers (MIM Capacitor and DMOS option) Core (I/O) voltage : 1.8 (3.3) V SOI wafer (200 mm f =8 inch) Top Si : Cz, ~18 -cm, p-type, ~40 nm thick Buried Oxide: 200 nm thick Handle wafer thickness: 725 mm  thinned up to 300 mm (Lapis) or ~50 mm (commercial process) Handle wafer type: NCZ, NFZ, PFZ, double SOI Backside process (2011~) Mechanical Grind Chemical Etching Back side Implant Laser Annealing  Al plating

Progress of SOI monolithic sensors 6/25 Progress of SOI monolithic sensors X-ray tube Target:Cr Integration-type pixel sensors (12mm pixel) (8mm pixel) beans Test chart 8mm slit screw X-ray phase-contrast image (INTPIX5) 16 keV monochromatic X-ray image (FPIX) CERN SPS NORTH H4-H6 p+ 55%, p 39%, K 5% CERN beam test in 2011 50mm-thick CZ INTPIX3e XRPIX3 30 mm pixel Kyoto Univ. S/N ~ 15 4 layers of INTPIX3e (16 mm pixel) Univ. of Tsukuba Energy loss

Pixel area (12mm pixel) 1408 x 1408 An example of Sensor layout (1) 7/25 An example of Sensor layout (1) HV ring (p+) INTPIX7 (MPW FY13-1) Integration-type pixel sensor Bias ring (n+) Min. ~ 275 mm Max. ~ 490 mm 18mm Pixel area (12mm pixel) 1408 x 1408 Pixel area N(0V) P(+HV) SiO2(yellow) 275-490 mm P- Enge of the chip (side view)

IO pad array Pixel area (12mm pixel) 1408 x 1408 8/25 An example of Sensor layout (2) 18mm INTPIX7 (MPW FY13-1) Pixel array Raw Address (RA) decoder Column Address (CA) decoder Column buffer, analog buffer, Bias circuit Pixel area (12mm pixel) 1408 x 1408 Decorder (RA) Pixel array Bias circuit Column Buffer Decorder (CA) IO pad array IO pad array

Pixel layout and circuit (1) INTPIX7 9/25 Pixel layout and circuit (1) INTPIX7 Pixel size 12mm CDS circuit in pixel Sense node Sense node 1 + Transistor 9 MIM capacitor 1 in 12 mm2 12mm

Pixel layout and circuit (2) FPIX 10/25 Pixel layout and circuit (2) FPIX Pixel size 8mm No STORE, no storage capacitor Sense node VDD COL_OUT READ_X (sensor) RST RST_x 8mm -V +V VRST Sense node 1+Transistor 6 In 8 mm2 GND Min. distance between sense node and transistor ~ 1mm

Current issues and solutions 11/25 Current issues and solutions SiO2 another SOI layer Buried P-Well (BPW) Si 1. BPW process : effective to analog circuit in a pixel 2. Double SOI wafer : effective to digital circuit in a pixel

12/25 Back-gate effect TCAD simulation HyENEXSS (TAC, Japan) MOS Tr Copyright 2007 Oki Electric Industry Co.,Ltd Threshold Variation Substrate Voltages act as Back Gate, and change transistor threshold.

Geometry of TCAD simulation for BPW effectiveness study 13/25 Dope density [/cm3] Geometry of TCAD simulation for BPW effectiveness study [mm] Lg = 0.3 Wg = 5 nmos 1mm source drain W Tsoi=40nm 1.1mm BOX 200nm p1 p2 Buried P-Well(BPW) (1e12-1e17) p+(1e20) p+(1e20) 5mm 15mm 260mm n- bulk (6e12) backbias 0-500V HyENEXSS (TAC, Japan)

Simulation result for BPW effectiveness study 14/25 Simulation result for BPW effectiveness study Dope density [/cm3] “Vth>0.4V” @ back bias > 100 V  p dose > 5e16 Increase of maximum voltage in which tr. works

Crosstalk study (TCAD Simulation) 15/25 Crosstalk study (TCAD Simulation) Transition analysis Blue: Vsource Black: Ip1 Red: Ip2 Single SOI w/o BPW Pulse 1V NMOS source Sense1,2 0.1mA 1ns Pulse 1V NMOS source Single SOI w. BPW 0.1mA Sense1 Sense2 1ns Crosstalk increase by BPW

An example of crosstalk observation (XRPIX2/2b,3/3b) 16/25 An example of crosstalk observation (XRPIX2/2b,3/3b) TIPP2014 A. Takeda (Kyoto Univ.) For X-ray astronomy Event-driven R/O circuit Comparator in pixel 30mm pixel Anti-coincidence (NXB rej.) Hit-pattern (NXB rej.) Direct pixel access (X-ray RO)

An example of crosstalk 17/25 An example of crosstalk XRPIX2/2b (Kyoto Univ.) A. Takeda,PIXEL2014 Sensor-circuit crosstalk? A large spike Due to Wiring of an analog and a trigger signal lines (100mV/div)

Double SOI pixel sensor 18/25 Double SOI pixel sensor STEM image SOI wafer Initial silicon * Substrate: NCZ or PCZ wafer Additional shield layer Shield the back gate effect Compensate effect of box charge Shield the sensor to circuit crosstalk

Geometry of TCAD simulation For double SOI effectiveness study 19/25 Geometry of TCAD simulation For double SOI effectiveness study Dope density [/cm3] [mm] Lg = 0.3 Wg = 5 nmos 1mm source drain Tsoi=40nm W 0V 1.1mm box SOI2 200nm p1 5mm 5mm p2 p+(1e20) p+(1e20) 5mm 15mm 260mm n- bulk (6e12)

Crosstalk (TCAD Simulation) 20/25 Crosstalk (TCAD Simulation) Transition analysis Blue: Vsource Black: Ip1 Red: Ip2 Pulse 1V at NMOS source Single SOI 0.1mA Sense1,2 1ns Pulse 1V at NMOS source Double SOI Sense1 0.1mA Sense2 Crosstalk can be suppressed in double SOI sensor

Development of double SOI pixel sensors 21/25 Development of double SOI pixel sensors 2012 The first prototype  breakdown study 2013 The second prototype  pixel sensor, rad. hard study (TIPP2014, VERTEX2014, IEEE-NSS 2014) 2014 The third prototype  Still under fabrication!  chips will be delivered in October

Y x Shaper output of beta-ray signal (PIXOR) Tohoku Univ. 22/25 Shaper output of beta-ray signal (PIXOR) Double SOI (d-SOI) : The second prototype Tohoku Univ. “Superpixel” includes pre-amp., shaper, discri. readout circuit Y x Y. Ono et al., NIMA 731 (2013) 266-269 N. Shinoda, Master thesis, March, 2013 Sr-90 beta-ray beta-ray signals were observed successfully from Pre-amp.&shaper cir. with d-SOI Discriminator output is not confirmed yet.

Future plan; Counting-type pixel (double SOI) 23/25 Future plan; Counting-type pixel (double SOI) Under development Test di sfto Ci[0:3] sclko Preamp. 15bit counter Discri. VTH Control register Test on/off Fine vth (3bit) P-type sensor (p- bulk) do sfti rst -Vdet sclki Co[0:3]

15bit counter Discri. Preamp. 24/25 Future plan; Counting-type pixel (double SOI) Under development SOI2 contact 15bit counter 50mm Sense node Discri. Control register Preamp.

Summary Several SOI pixel sensors have successfully been fabricated 25/25 Summary Several SOI pixel sensors have successfully been fabricated 3 issues; the back-gate effect, radiation hardness, sensor-circuit crosstalk 1. The back-gate effect Integration-type pixel sensors works thanks to BPW process 2. Sensor-circuit crosstalk can be suppressed by applying double SOI 3. Radiation hardness (is not mentioned in this talk) Double SOI pixel sensors: The 1st trial 2012 The 2nd trial 2013 The 3rd trial 2014 Chips will be delivered in October. optimize pixel design with p-type DSOI sensors SPRiT (SOI Portable Radiation imaging Terminal) http://rd.kek.jp/project/soi/

Supplement

Various Implantation Options in Sensor part CPIX14 Y.Arai SOI process

Requirements to the Pixel Detectors Hadron colliders: High total integrated dose and neutron flux LHC ATLAS inner Pixel detector: ~160 kGy and 1015 neq/cm2 (x10 for HL-LHC) Immunity to Single Event Effects Very high event pile-up Linear colliders: High granularity Complex readout scheme SOI pixel detector fulfill these requirements. ATLAS Luminosity Public Results: https://twiki.cern.ch/twiki/bin/view/AtlasPublic/LuminosityPublicResults M. Yamada, PIXEL2014 2014/09/01 PIXEL2014

Cancelling the TID effects M. Yamada, PIXEL2014 Cancelling the TID effects Univ. Tsukuba Compensation of TID effect Threshold of transistor shifts negatively due to positive potential from BOX . Applied negative potential to SOI2 (VSOI2). Test samples (NMOS and PMOS) several L and W of Tr low, normal and high threshold V Three kinds of body connections Several types of transistors are used for readout circuit. We evaluated the radiation damage of transistors processed on double SOI. After irradiation, threshold of transistor shifts negatively due to positive potential from BOX To compensate this TID effect, we applied negative potential to second silicon layer, its called VSOI2 in this talk. We tested some types of transistors, which are several L and W, low, normal and high threshold voltage and three kinds of body connections, are processed on SOI wafer before and after irradiation of 60Co gamma ray from 3kGy up to 2 MGy. Top right figure shows the threshold voltage of transistor. Dashed line indicates the threshold voltage before irradiation. As you can see we succeeded to recover threshold to apply negative voltage to SOI2 layer. Threshold recovered within in plus minus 0.05 V for NMOS shown in right figure and plus minus 0.1 V for PMOS with optimum VSOI2. However different VSOI2 settings need to compensate the TID for each type of transistor. (BF) (S-TIE/S-TIE2) (MULTIB-TIE) Irradiation: 60Co 𝛾-ray from 3 kGy up to 2 MGy at Takasaki Advanced Radiation Research Institute, JAEA (http://www.taka.jaea.go.jp/index_e.html) 2014/09/01 PIXEL2014

ID-VG after Irradiation with VSOI2 M. Yamada, PIXEL2014 ID-VG after Irradiation with VSOI2 Univ. Tsukuba ID-VG curves with VSOI2 to cancel positive potential from BOX after irradiation of 200 kGy. NMOS Body-tie PMOS Body-tie Vth Recover Vth Recover ●VSOI2=0V ●VSOI2=-1V ●VSOI2=-2V ●VSOI2=-3V ●VSOI2=-4V ●VSOI2=-5V ●VSOI2=-10V●VSOI2=-15V We observed recovery of ID-VG curve after irradiation with VSOI2. 2014/09/01 PIXEL2014

Double SOI M. Yamada, PIXEL2014 Univ. Tsukuba Pre-irrad Response to infrared laser of 1064 nm wavelength and 10 ns pulse duration. VSOI2=0V VSOI2=-10V The pixel images after 100 kGy could not obtain but recovered with VSOI2=-10V. The average ADC count as function of the square root of the bias voltage for sensor. Obtained similar linearity and sensitivity to pre-irradiation with VSOI2=-10 V . And one more additional test, response to infrared laser of 1064 nm wavelength and 10 ns pulse duration tested. Shown in top right figure, we can see the response to infrared laser before irradiation. After irradiation we could not obtain the pixel images but recovered to apply VSOI2 of -10V. And the average ADC count as function of the square root of the bias voltage for sensor checked. The sample irradiated to 100 kGy with VSOI2 of -10V obtained similar linearity and sensitivity to pre-irradiation. Other tests are still working in progress and we expect the double SOI process compensate the TID effect. S. Honda et al., TIPP12014, 2-6 June 2014, Amsterdam 2014/09/01 PIXEL2014

TID: Target Radiation Levels K. Hara, VERTEX2014 TID: Target Radiation Levels SOI is immunity from SEEs for smaller active area, enclosed in oxide layers ideal for space applications 50nm 200nm ~100um TID: Total Ionization Damage is rather complicated … Wide dose range of applications: LHC pixel ~ 500 kGy, 1015neq/cm2@ATLAS　(x10 for HL-LHC) Belle-II ~ 10 kGy/y, 2x1012neq/cm2 /y ILC (e.g., ILD @ r=15 mm) ~ 1 kGy/y, ~1011neq/cm2 /y X-ray imaging: kGy/y ～MGy/y … Radiation damage studies done so far: proton irradiation to 1016 neq/cm2 60Co γ irradiation to 5 MGy for DOUBLE-SOI: 60Co γ irradiation to 2MGy K. Hara, VERTEX2014, Macha Lake, Czech Sep.16-19

PIXOR M. Yamada, PIXEL2014 Tohoku Univ. Digital part It manages holding of binary data from discriminator and timing comparison of hit and trigger. Generally a trigger decision takes several micro seconds from the actual event time in high energy experiment (trigger latency). Evaluated the overall circuit of digital part with a test-pulse. Clock Trigger latency Trigger latency Digital circuit could store the hit information of the signal during the trigger latency and sent a binary hit information as expected. Y. Ono et al., NIMA 731 (2013) 266-269 N. Shinoda, Master thesis, March, 2013 2014/09/01 PIXEL2014

PIXOR Vertex Detector of Belle II Two layers of pixel detector DEPFET M. Yamada, PIXEL2014 PIXOR Vertex Detector of Belle II Two layers of pixel detector DEPFET Four layers of silicon strip detector SVD SVD DEPFET We are aiming PIXOR is installed as 1st layer of SVD for Belle II upgrade. M.Friedl et al., “The Silicon Vertex Detector of Belle II”, VERTEX2011, 19-24 June 2011, Rust, Lake Neusiedel, Austria 2014/09/01 PIXEL2014