Silicon Tracker Data Acquisition and Electronics for the Linear Collider Jean-Francois Genat LPNHE Universite Pierre et Marie Curie CNRS/IN2P3 On behalf of: Philippe Bailly, Jean-Francois Genat, Herve Lebbolo, Olivier Le Dortz, Michele Detournai, and Aurore Savoy-Navarro ECFA Linear Collider Workshop, Durham UK, Sept. 3d 2004

Output signals: very preliminary exercise Exercise performed with 3 external layers of a Silicon tracker: Multiplex as much as possible the output signals from the detector At the digitization stage: highly multiplexed A/D scheme

Context All Silicon Tracker envelope: few 100m 2, a few 10 6 strips Asynchronous events: ~ 1 ms Data taking/pre-processing ~ 200 ms Occupancy: Assume < a few % Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

The readout of the Si-tracker - Detector occupancy: Outer central region: Preliminary studies: < 1 % Inner central and forward regions: Preliminary studies: < 10%  Work in progress with Geant - Double & Multiple hit rates: Ambiguities to be estimated: tiling vs long strips - Sparsification/pedestal substraction:  On the detector FE - Pulse height needed: Cluster centroid to improve position resolution to 7–8 µ m  A 10 bit A/D under construction - Timing information Included in the FE design. The principle & possible performances are being studied  Paris test bench - Digital processing for cluster algorithm and fast-track processing algorithm.  Under study while designing FE - Power dissipation studies: Present results do not anticipate a major pb  passive (or light) cooling might be achievable.  FE Power cycling Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

Goals: Low noise preamplifiers Long shaping time Time measurement Very low power dissipation Shared ADC/TDC sparsification Power cycling Compact and transparent Choice of DSμE

Front-end processing Time: Disc, Digital delay Storage Compaction Time, Charge Technology: Deep Sub-Micron CMOS UMC 0.18  m Faster and less 1/f noisy alternative: Silicon-Germanium Charge: PA shaper, S&H, Disc Counter ADC (To Trigger) Ch # Readout (From Trigger) Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004 Charge 1-45 MIP, S/N~40, Time 1ns Calibration Control Amplification + long shaping + storage + time tagging S&H: digitization

Analog Charge Preamp C f = 400 fF CR-RC Shaper Sample and Hold High threshold Low threshold Digital delay Charge Time Hold Input N.B: The time measurement will not be included in the first FE design. It will be first experienced on the Lab test bench. Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

Preamp Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

Deep Sub-Micron CMOS 0.18  m technology Preamp - Shaper MIP - Gain 8 mV/MIP  W/ch If 100 MIPS needed, just twice preamp power - 4  s conversion time - 10 bits (500 MHz internal clock) - 40  W/ch ADC Timing - Two-threshold discriminator - 60  W Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

Performance - Noise: - Preamp + 5  s shaping time, 50 pF detector (no leak, no bias resistor): simulated 690 e- ENC S/N ~ 40 Gain 8mV/MIP - Power: - Preamp + Shaper + timing Preamp: 85  W Shaper: 110  W Timing: 60  V - Shared ADC/TDC ADC: 40  W Total: 295  W/channel Power Switching: If Preamp –Shaper +ADC are running during collisions only: e.g. 1/100 duty cycle and channels, then: Total: x x = 7.7 Watts only ! Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

Preamp Linearity Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d Linearity better than ± 5‰

Shaper response Gain: 8mV/MIP over 45 MIP 5 MIP/step Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

Noise Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004 If 1/f noise shows up at 5  s shaping, consider Silicon-Germanium technology

Preamp Power Switching - Reset the feedback capacitor after switching on and before switching off (Takes 5 us) - Open and close two switches feeding Vdd Vss ( Ron~=100  ) Power is zero when switched off Power offPower onPower offPower on Reset Feedback Capacitor Signal Vdd Vss Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

ADC Comparator: Time Walk simulations Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d Linearity better than ± 5‰ 0

Digital - TDC counter - ADC coding - Memory - Zero suppression and lossless data compression - Calibration management Tools: - Virtual Silicon Library for UMC 0.18  m - I/O pads - VHDL/Verilog - Synthesizer interface (Ambit) - Cadence Silicon Ensemble for digital layout - Merge manually analog and digital cells Help from Erwin Deumens at IMEC (Leuven) Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

Layout 16 analog charge channels: - 60  m pitch, - I/O pad, preamp, shaper, sample & hold, comparator - Full prototype chip including digital fits in 2.2 mm 2 1mm 0.75mm Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

Silicon UMC 0.18  m Europractice (Leuven) - Standard 5 x 5 mm 2 or 2.2 x 2.2 mm 2 (sharing possible) One full analog channel (including I/O) pad is 60 x750  m 2 =.045 mm 2 only Full 128 channels chip may fit in less than 25 mm 2 (SVX4 in TSMC 0.25 is ~60 mm 2 for 128 channels including analog pipe-lines, ADC, I/O) - Submission at Europractice: next UMC run mid October Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004

Conclusion Emerging new VLSI technologies: - Silicon Deep Sub Micron CMOS - Silicon-Germanium alternative (incorporate DSM CMOS) allow to implement a highly integrated front end for SiLC that does not degrade the detector resolution, both in time and amplitude within an affordable power and material budget and implement system integration such as data compaction, cluster centroid, fast tracking algorithms Jean-Francois Genat, ECFA Linear Collider Workshop, Durham, September 3d 2004