DIGITAL LOGIC CIRCUITS 조수경 DIGITAL LOGIC CIRCUITS

CONTENTS 1.BASIC LOGIC BLOCK 2.FILP-FLOPS(F/F) 3.DIFFERENCE OF LATCH & F/F 4.Master-Slave F/F 5.CLOCK PERIOD 6.SEQUENTIAL CIRCUITS 1.REGISTERS 2.COUNTERS * LOGIC CIRCUIT DESIGN EXAMPLE DIGITAL LOGIC CIRCUITS

BASIC LOGIC BLOCK Combinational Logic Block –Output value decided by the current input value. –There is no memory cell. –MUX, Encoder, Decoder, Parity Checker, Parity Generator, etc. Sequential Logic Block –Output value decided by 2 values. The current input value and state value of the block. –There is memory cell. –F/F Memory cell’s feedback line DIGITAL LOGIC CIRCUITS

CLOCKED F/F DIGITAL LOGIC CIRCUITS

LATCH? FLIP FLOPS? Latches Positive Edge-triggered F/F DIGITAL LOGIC CIRCUITS

Master-Slave F/F Act when CP is rising or falling. Master slave JK F/F is prevent about race around. SR2 Inactive SR1 Active SR2 Active SR1 Inactive SR2 Inactive SR1 Active SR1 SR DIGITAL LOGIC CIRCUITS

SR2 Inactive SR1 Active SR2 Active SR1 Inactive SR2 Inactive SR1 Active SR1 SR DIGITAL LOGIC CIRCUITS

Clock Period CLOCK PERIOD T = CPU 속도의 역수 = t d + t s + t h Setup timeHold time DIGITAL LOGIC CIRCUITS

Sequential Circuits - Register DIGITAL LOGIC CIRCUITS

Sequential Circuits - Counter DIGITAL LOGIC CIRCUITS

LOGIC CURCUIT DESIGN EXAMPLE DIGITAL LOGIC CIRCUITS

THANK YOU DIGITAL LOGIC CIRCUITS