Introduction to microfabrication, chapter 1 Figures from: Franssila: Introduction to Microfabrication unless indicated otherwise.

Slides:



Advertisements
Similar presentations
MICROELECTROMECHANICAL SYSTEMS ( MEMS )
Advertisements

FABRICATION PROCESSES
CMOS Fabrication EMT 251.
Lecture 0: Introduction
VLSI Design Lecture 2: Basic Fabrication Steps and Layout
Fabrication of p-n junction in Si Silicon wafer [1-0-0] Type: N Dopant: P Resistivity: Ω-cm Thickness: µm.
Introduction to CMOS VLSI Design Lecture 0: Introduction
Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice.
IC Fabrication and Micromachines
Device Fabrication Technology
The Physical Structure (NMOS)
Process integration
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #5.
Device Fabrication Example
Introduction Integrated circuits: many transistors on one chip.
ECE685 Nanoelectronics – Semiconductor Devices Lecture given by Qiliang Li.
Introduction to microfabrication, chapter 1
Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-1  10 Micrometer Design Rules  4 Design Layers.
ES 176/276 – Section # 2 – 09/19/2011 Brief Overview from Section #1 MEMS = MicroElectroMechanical Systems Micron-scale devices which transduce an environmental.
Z. Feng VLSI Design 1.1 VLSI Design MOSFET Zhuo Feng.
CS/EE 6710 CMOS Processing. N-type Transistor + - i electrons Vds +Vgs S G D.
Fabrication of Active Matrix (STEM) Detectors
Why do we put the micro in microelectronics?. Why Micro? 1.Lower Energy and Resources for Fabrication 2.Large Arrays 3.Minimally Invasive 4.Disposable.
Integrated Circuit Devices Professor Ali Javey Summer 2009 Fabrication Technology.
1. A clean single crystal silicon (Si) wafer which is doped n-type (ColumnV elements of the periodic table). MOS devices are typically fabricated on a,
Chapter 4 Overview of Wafer Fabrication
Gas-to Solid Processing surface Heat Treating Carburizing is a surface heat treating process in which the carbon content of the surface of.
Semiconductor Manufacturing Technology Michael Quirk & Julian Serda © October 2001 by Prentice Hall Chapter 9 IC Fabrication Process Overview.
SEMINAR PRESENTATION ON IC FABRICATION PROCESS
Introduction to CMOS VLSI Design CMOS Fabrication and Layout Harris, 2004 Updated by Li Chen, 2010.
By: Joaquin Gabriels November 24 th,  Overview of CMOS  CMOS Fabrication Process Overview  CMOS Fabrication Process  Problems with Current CMOS.
Thermal doping review example This presentation is partially animated. Only use the control panel at the bottom of screen to review what you have seen.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 3, slide 1 Introduction to Electronic Circuit Design.
IC Processing. Initial Steps: Forming an active region Si 3 N 4 is etched away using an F-plasma: Si3dN4 + 12F → 3SiF 4 + 2N 2 Or removed in hot.
ISAT 436 Micro-/Nanofabrication and Applications Photolithography David J. Lawrence Spring 2004.
CORPORATE INSTITUTE OF SCIENCE & TECHNOLOGY, BHOPAL DEPARTMENT OF ELECTRONICS & COMMUNICATIONS NMOS FABRICATION PROCESS - PROF. RAKESH K. JHA.
Substitute beer and pizza?. Basic Silicon Solar Cell as fabricated in Cameron With Schematic.
©2008 R. Gupta, UCSD COSMOS Summer 2008 Chips and Chip Making Rajesh K. Gupta Computer Science and Engineering University of California, San Diego.
Microfabrication CHEM-E5115
CMOS VLSI Fabrication.
CMOS FABRICATION.
Process integration Wafer selection active role for the wafer ? passive role ? –thermal conductivity –optical transparency –flat,
Thin films
Antenna Project in Cameron clean room Wafer preparation, conductor deposition, photolithography.
Patterning - Photolithography
CMOS Fabrication EMT 251.
CMOS VLSI Design Lecture 2: Fabrication & Layout
Microfabrication for fluidics, basics and silicon
1. Introduction. Diseño de Circuitos Digitales para Comunicaciones Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration.
Wafer bonding (Chapter 17) & CMP (Chapter 16)
Process integration 1: cleaning, sheet resistance and resistors, thermal budget, front end
CMOS Fabrication CMOS transistors are fabricated on silicon wafer
Prof. Jang-Ung Park (박장웅)
Microfabrication Home exercise 1
Microfabrication CHEM-E5115 sami. fi victor
Manufacturing Process I
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 3-1 Chapter 3 Device Fabrication Technology About transistors (or 10 billion for.
Chapter 1 & Chapter 3.
VLSI System Design LEC3.1 CMOS FABRICATION REVIEW
Silicon Wafer cm (5’’- 8’’) mm
Lecture #25 OUTLINE Device isolation methods Electrical contacts to Si
Process flow part 2 Develop a basic-level process flow for creating a simple MEMS device State and explain the principles involved in attaining good mask.
Manufacturing Process I
Device Fabrication And Diffusion Overview
Manufacturing Process I
Device Fabrication And Diffusion Overview
CSE 87 Fall 2007 Chips and Chip Making
Presentation transcript:

Introduction to microfabrication, chapter 1 Figures from: Franssila: Introduction to Microfabrication unless indicated otherwise.

Dimension in microworld Fig. 1.12

Fig. 1.3: Electron beam lithography defined gold-palladium nanobridge Microfabrication vs. Nanofabrication ? Fig. 24.4: Focussed ion beam patterned Aalto vase

Materials substrate thin film 2 surface interface 2 interface 1 Substrate: thick piece of material (0.5 mm = 500 µm) Thin films: nm; silicon most often Fig. 1.5 thin film 1

Common materials Substrates: Silicon (glass) Thin films: SiO 2 SiN x Polysilicon Al Cu W Pt Others: Photoresist

The most common film: SiO 2 Si O2O2 O2O2 O2O2 O2O2 O2O2 O2O2 Thermal oxidation Si SiO o C 1 µm 500 µm

SiO 2 thin films: 2 cases Si O2O2 O2O2 O2O2 O2O2 O2O2 W 1000 o C ? Si O2O2 O2O2 O2O2 O2O2 400 o C Al ?

Solution: CVD Si O2O2 O2O2 SiH 4 O2O2 400 o C SiH 4 Al Si SiH 4 SiH 4 + O 2  SiO 2 + 2H 2 SiO 2 CVD = Chemical Vapor Deposition

Patterning: lithography and etching Fig. 9.1

Photoresist exposure Positive resist: exposed parts become soluble Negative resist: exposed parts cross- linked and insoluble photomask photoresist UV light silicon wafer Fig. 9.10

After lithography ab c de f a)ion implantation (Ch 15) b)wet etching (Ch 11) c)moulding (Ch 18) d)plasma etching (Ch 11) e)electroplating (Ch 29) f)lift-off (Ch 23) Fig. 9.14

Doping backside metallization top metallization antireflection coating ( ARC ) p-substrate p+ diffusion n -diffusion Doping can change resisitivity dramatically, and even change dopant type from p to n and vice versa. Original wafer: p-substrate (e.g cm -3 boron) n-diffusion (e.g cm -3 phosphorous) p+ diffusion (e.g cm -3 boron) Fig. 25.2

P-type silicon substrate (boron majority) boron phosporousimpurities

Phosphorous diffusion  top layer turned into n-type Bulk of the wafer remains p-type, because diffusion does not extent to depth of wafer.

Junction depth x j X j is the depth where diffused dopant concentration equals wafer dopant concentration (of opposite type). x j ≈ 1.2 µm C dopant cm cm cm depth/µm

Silicon wafers scribe lines for chip dicing wafer flat for orientation checking alignment marks for lithography edge exclusion Fig Real estate allocation on a wafer Fig. 1.4: 100 mm diameter silicon wafer

Silicon strengths silicon is a good mechanical material silicon is good thermal conductor silicon is transparent in infrared silicon is a semiconductor silicon is optically smooth and flat silicon is known inside out  consider silicon first, alternatives then

Single crystalline silicon (a.k.a. monocrystalline) silicon Fig. 4.6

Polycrystalline and amorphous materials Fig. 1.6

Fig. 1.1: Microtechnology subfield evolution from 1960’s onwards.

Silicon microelectronics 0.5 µm CMOS in SEM micrograph65 nm CMOS in TEM micrograph Fig. 1.15Fig. 1.11

Optoelectronics Fig. 1.14: Silicon solar cell Fig. 6.2: GaAs multiple quantum well solar cell

MEMS: Micro Electro Mechanical Systems Fig : Microgears, courtesy Sandia National Labs. Fig. 21.3: comb-drive actuator

Power MEMS Fig. 1.17: Microturbine Fabricated by bonding together 5 silicon wafers.

MOEMS (Micro Opto Electro Mechanical Systems) Fig. 1.2: Micromirror made of silicon, 1 mm diameter, is supported by 1.2 µm wide, 4 µm thick torsion bars (detail figure), from ref. Greywall. Fig. 21.4: variable optical attenator

Micro-optics Fig. 1.7: Aluminum oxide and titanium oxide thin films deposited over silicon waveguide ridges, courtesy Tapani Alasaarela. Fig. 7.13: Refractive index SiO 2 /SiO x N y /SiO 2 waveguide: n f 1.46/1.52/1.46. From ref. Hilleringmann.

Microfluidics and BioMEMS Fig. 1.13: silicon microneedle Fig. 1.11: Oxy-hydrogen burner flame ionization detector

Cleanroom Fig. 1.19

Yield Yield of a total process is a product of yield of individual process steps 50 step MEMS process Y 0 =  95% 500 step DRAM process, Y 0 =  61%

Yield (2) Yield depends on chip area (A) and defect density (D) D = 0.01 mm -2 (= 1/cm 2 ) A= 10 mm 2  Y = 90% A= 100 mm 2  Y = 37%

Microindustries are big Integrated circuits$330 B Other semiconductors$30 B Flat panels displays$130 B Solar cells$100 B Hard disks$30 B MEMS$10 B Equipment$60 B Materials$10 B