DEPARTMENT OF ELECTRONICS ENGINEERING v-semester MICROPROCESSOR & MICROCONTROLLER CHAPTER NO.4 Numeric Co-processor & DMA Controller

CHAPTER 4:- SYLLABUS 1 Topic 1: 8086 maximum mode pin diagram 2 . Topic 1: 8086 maximum mode pin diagram 1 Topic 2: Closely coupled & loosely coupled multiprocessor system 2 Topic 3: 8087 Numeric coprocessor, architecture, interfacing with 8086, instruction set. 3 Topic 4: DMAC 8237, Architecture, Interfacing & programming 4 Topic i5: Introduction to Pentium 5 DTEL 2

CHAPTER-4 SPECIFIC Objective / course outcome The student will be able to: Understand 8086 maximum mode 1 Learn DMAC 8237 ,it’s Architecture & Interfacing 2 Learn 8087 Numeric coprocessor, it’s architecture & interfacing with 8086. . 3 Get introduction of advancement in 8086 i.e. Pentium series. 4 DTEL 3

Figure 4.1: 8086/8088 Pin Configuration LECTURE 33:- 8086 Maximum Mode 4 Figure 4.1: 8086/8088 Pin Configuration DTEL 4

Figure 4.2: 8086/8088 Pin Configuration Differences LECTURE 33 8086 Maximum Mode 5 Figure 4.2: 8086/8088 Pin Configuration Differences DTEL 5

Why we need a math coprocessor? LECTURE 33:- The 8087 Math Coprocessor Why we need a math coprocessor? Using a general-purpose microprocessor such as the 8088/86 to perform mathematical functions such as log, sine, and others is very time consuming, not only for the CPU but also for programmers writing such programs. In the absence of a math coprocessor, programmers must write subroutines using 8088/86 instructions for mathematical functions. 6 DTEL 6

The 8087 Math Coprocessor LECTURE 33:- In some cases the differences of run times is hours between PCs with and without math-coprocessor. Table No. 4.1:- Comparison of 8087 & 8086 clock times 7 DTEL 7

LECTURE 33:- THANK YOU DTEL 8

LECTURE 34:- The 8087 Math Coprocessor 9 DTEL 9

The following is description of the signal connection. LECTURE 34:- The 8087 Math Coprocessor The following is description of the signal connection. The 8088 and 8087 receive the same signals, CLK, READY, and RESET, from the 8284. This ensures that they are synchronized. 2. S0, S1, and S2 are going from the 8088 or 8087 to the 8288, which allows either of these two processors to provide the status signal to the 8288. 3. The Queue Status, QS1 and QS2, from the 8088 go to the 8087, allowing it to know the status of the queue of the 8088 at any given time. 10 DTEL 10

The 8087 Math Coprocessor Continue…… LECTURE 34:- 4. The TEST signal to the 8088 comes from BUSY of the 8087. By deactivating (going low) the BUSY signal, the 8087 informs the 8088 that it finished execution of the instruction which it has been Waiting for. 5. RQ/GT1 (request/grant) of the 8088 is connected to RQ/GTO of the 8087, allowing them to arbitrate mastery over the buses. There are two sets of RQ/GT: RQ/GT1 and RQ/GTO . RQ/GT1 of the 8087 is not used and is connected to VCC permanently. This extra RQ/GT is provided in case there is a third microprocessor connected to the local bus. 11 DTEL 11

The 8087 Math Coprocessor Continue… LECTURE 34:- 6. Both the 8088 and 8087 share buses ADO -AD7 and A8 -A19, allowing either one to access memory. Since the 8087 is designed for both the 8088 and 8086, signal BHE is provided for the 8086 processor. It is connected to VCC if the 8087 is used with the 8088. If the microprocessor used was an 8086, BHE from the 8086 is connected to BHE of the 8087. 12 DTEL 12

The 8087 Math Coprocessor Continue… LECTURE 34:- 7. INT of the 8087 is an output signal indicating error conditions, also called exceptions, such as divide by zero. Error conditions are given in the status word. Assuming the bit for that error is not masked and an interrupt is enabled, whenever any of these errors occurs, the 8087 automatically activates the INT pin by putting high on it. In the IBM PC and compatibles, this signal is connected to the NMI circuitry. Since there is only one INT for all error conditions (exceptions) of the 8087, it is up to the programmer to write a program to check the status word to see which has caused the error. 13 DTEL 13

The 8087 Math Coprocessor Continue… LECTURE 34:- 8. The 8088, often called the host processor, must be connected in maximum mode to be able to accommodate a coprocessor such as the 8087. Continue… 14 DTEL 14

LECTURE 34:- THANK YOU DTEL 15

Reading an operand by the coprocessor LECTURE 35:- The 8087 Math Coprocessor Reading an operand by the coprocessor Assume that the 8087 needs to read an operand. When the 8088/86 initiates the operand read cycle, the 8087 grabs the 20-bit address and saves it internally. If the operand is a single word (like a word integer), the read cycle has been initiated and the word will come into both processors. Only the 8087 will use the data; the 8088/86 will ignore it. However, if the operand is 32 bits or longer, the 8087 will take over the buses by sending a low pulse on its RQ/GTO to the RQ/GT1 of the 8088/86 (see Figure 20-4). 16 DTEL 16

Reading an operand by the coprocessor LECTURE 35:- The 8087 Math Coprocessor Reading an operand by the coprocessor The 8088/86 in turn will send back a low pulse through the same pin, thereby allowing the 8087 to take over the buses. Remember, RQ/GT is a bidirectional bus. When the 8087 takes over the buses, it will use them until it brings in the last byte of the operand. It is only then that by activating RQ/GT (making it low), control of the buses is given back to the 8088/86. For example, in the case of a DT operand, the 8087 has control over the buses for the time needed to fetch all 10 bytes and then it gives back the buses. 17 DTEL 17

Writing an operand by the coprocessor LECTURE 35:- The 8087 Math Coprocessor Writing an operand by the coprocessor In the case of writing an operand by the coprocessor (e.g., FST data), the 8088/86 initiates the write cycle, but the 8087 ignores it since the 8086 does not have the operand. This is called a dummy cycle. All the 8087 does during the dummy cycle is grab the address of the first memory location where the operand is to be stored and keep it until the data is ready, and then it requests the use of the buses by activating the RQ/GT pin. 18 DTEL 18

Writing an operand by the coprocessor LECTURE 35:- The 8087 Math Coprocessor Writing an operand by the coprocessor From then on, the process is the same as the read cycle, meaning that it will use the buses until it writes the last byte of the operand. All the cases discussed so far have been taken care of by either the assembler or the hardware and there was no need for the programmer to be worried. 19 DTEL 19

8087 control and status words LECTURE 35:- The 8087 Math Coprocessor 8087 control and status words 20 Figure 4.4:-8087 control and status words DTEL 20

LECTURE 35:- THANK YOU DTEL 21

8237 Direct memory access Controller LECTURE 36:- 8237 Direct memory access Controller Direct memory access (DMA) is a process in which an external device takes over the control of system bus from the CPU. DMA is for high-speed data transfer from/to mass storage peripherals, e.g. hard disk drive, magnetic tape, CD-ROM, and sometimes video controllers. For example, a hard disk may boasts a transfer rate of 5 M bytes per second, i.e.1 byte transmission every 200 ns. To make such data transfer via the CPU is both undesirable and unnecessary. 22 DTEL 22

8237 Direct memory access Controller LECTURE 36 :- 8237 Direct memory access Controller The basic idea of DMA is to transfer blocks of data directly between memory and peripherals. The data don’t go through the microprocessor but the data bus is occupied. “Normal” transfer of one data byte takes up to 29 clock cycles. The DMA transfer requires only 5 clock cycles. Nowadays, DMA can transfer data as fast as 60 M byte per second. The transfer rate is limited by the speed of memory and peripheral devices. 23 DTEL 23

Basic process of DMA 8237 Direct memory access Controller LECTURE 36:- For 8088 in maximum mode: The RQ/GT1 and RQ/GT0 pins are used to issue DMA request and receive acknowledge signals. Sequence of events of a typical DMA process 1) Peripheral asserts one of the request pins, e.g. RQ/GT1 or RQ/GT0 (RQ/GT0 has higher priority) 2) 8088 completes its current bus cycle and enters into a HOLD state 3) 8088 grants the right of bus control by asserting a grant signal via the same pin as the request signal. 4) DMA operation starts 5) Upon completion of the DMA operation, the peripheral asserts the request/grant pin again to relinquish bus control. 24 DTEL 24

Basic process of DMA 8237 Direct memory access Controller LECTURE 36:- For 8088 in minimum mode: The HOLD and HLDA pins are used instead to receive and acknowledge the hold request respectively. Normally the CPU has full control of the system bus. In a DMA operation, the peripheral takes over bus control temporarily. 25 DTEL 25

LECTURE 36:- THANK YOU DTEL 26

DMA controller 8237 Direct memory access Controller LECTURE 37:- A DMA controller interfaces with several peripherals that may request DMA. The controller decides the priority of simultaneous DMA requests communicates with the peripheral and the CPU, and provides memory addresses for data transfer. DMA controller commonly used with 8088 is the 8237 programmable device. 27 DTEL 27

DMA controller 8237 Direct memory access Controller LECTURE 37:- The 8237 is in fact a special-purpose microprocessor. Normally it appears as part of the system controller chip-sets. The 8237 is a 4-channel device. Each channel is dedicated to a specific peripheral device and capable of addressing 64 K bytes section of memory. 28 DTEL 28

8237 Direct memory access Controller LECTURE 37:- 8237 Direct memory access Controller 29 Figure 4.5: Interconnection of 8237 DMA controller with 8086 DTEL 29

8237 Direct memory access Controller LECTURE 37:- 8237 Direct memory access Controller 30 Figure 4.6: Block diagram of 8237 DTEL 30

8237 Direct memory access Controller LECTURE 37:- 8237 Direct memory access Controller 31 Figure 4.7: Interconnection of 8237 DMA controller with 8086 DTEL 31

Pentium microprocessors LECTURE 37:- Pentium microprocessors A 32-bit microprocessor introduced by Intel in 1993. It contains 3.3 million transistors, nearly triple the number contained in its predecessor, the 80486 chip. The Pentium processor has been superseded by the Pentium Pro and Pentium II microprocessors. Since 1993, Intel has developed the Pentium III and more recently the Pentium 4 microprocessors. DTEL 32

Pentium microprocessors-III LECTURE 37:- Pentium microprocessors-III Intel builds on the technology it developed with the Pentium II microprocessors. The Pentium III processor comes with a Synchronized Dynamic Random Access Memory (SDRAM), allowing for an extremely fast transfer of data between the microprocessor and the memory. 70 new instructions, called Streaming SIMD Extensions, enhance multimedia and 3D performance. An advanced transfer cache and system buffering are able to meet higher data bandwidth requirements. DTEL 33

Pentium microprocessors-III LECTURE 37:- Pentium microprocessors-III Launched February 1999 - Available in speed levels of 450, 500, 550, and 600MHz .25 Micron Manufacturing Process 32KB of Level 1 Cache (operating at CPU's full core speed) 512KB of Level 2 Cache (operating at ½ of CPU's core speed) 100 MHz front-side bus speed MMX support The branch prediction/recovery pipeline was doubled to include 10-stages from the P-II DTEL 34

Pentium microprocessors -4 LECTURE 37:- Pentium microprocessors -4 The next generation of microprocessors from Intel. Pentium 4 is the product of a serious redesign. The move from Pentium II to Pentium III added two million transistors. The Pentium 4 sports a whopping 42 million - 14 million more than the currently available Pentium III Coppermine processors. (Actually, 55 million for redundancy/reliability.) DTEL 35

Pentium microprocessors-4 LECTURE 37:- Pentium microprocessors-4 The Pentium 4 is significantly larger than its predecessor. The P4 was first etched using the same .18-micron, aluminum trace process as the P-III Coppermine. The current P4 etching is the .13-micron process Now that the Pentium 4 is upon us the pipeline depth has been doubled once again to 20 stages – Net Burst micro architecture . By doubling the depth of the branch prediction pipe, the penalty associated with miss-predictions is greatly increased This results in a lower average number of instructions successfully executed per clock cycle. DTEL 36

Pentium microprocessors-4 LECTURE 37:- Pentium microprocessors-4 To compensate for the lower IPC, Intel has implemented: Execution Trace Cache Dynamic Execution Engine A 32-bit microprocessor, hyper-pipelined technology, a rapid execution engine and a quad-pumped 100MHz-system bus, delivering the equivalent of 3.2GB/s of bandwidth- three times the bandwidth of the Pentium III It transfers data at the equivalent of 400MHz bus speed DTEL 37

Pentium microprocessors-III LECTURE 37:- Pentium microprocessors-III Figure 4.8: Circuit arrangement of P-3 Microprocessor DTEL 38

Pentium microprocessors-4 LECTURE 37:- Pentium microprocessors-4 The next generation of P4 processors will use .09 microns trace process technology. That is 90 nanometers (90 billionths of a meter) We are beginning to reach the limits of Silicon based chips. Next step may be nanotechnology DTEL 39

Chapter 4 Question Bank LECTURE 37:- State the definition of 8086 in maximum mode. What are the functions provided by8288 bus controller in maximum ode of 8086 system?? Explain with the neat diagram all data types of 8087 with suitable example. Explain the status register of 8087. Draw the interconnection of 8087 with 8086. Explain with the neat diagram, the operation of 8237 DMA controller. Data transfer between memory to memory is possible using 8237. Justify it. Draw 8088-8237 interface and explain DMA read operation.

LECTURE 37:- Summary There are two operating modes of 8086 as Minimum mode & Maximum mode. When MN/MX =0, maximum mode is selected and this mode is used when more than one processor have to use in a system. 8087 is an numeric data processor. It supports 7 data types. 8087 adds Arithmetic, Trigonometric, Exponential & Logarithmic instructions to standard 8086 instruction set of all data types. (8237) Direct memory access (DMA) is a process in which an external device takes over the control of system bus from the CPU. It is used for high-speed data transfer from/to mass storage peripherals, e.g. hard disk drive, magnetic tape, CD-ROM, and sometimes video controllers. The HOLD and HLDA pins are used in minimum mode instead to receive and acknowledge the hold request respectively as in maximum mode. In a DMA operation, the peripheral takes over bus control temporarily.

LECTURE 37:- THANK YOU DTEL 42