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Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz.

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Presentation on theme: "Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz."— Presentation transcript:

1 Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz

2 Many processors include registers, known as the PSW, which contain status information such as condition codes plus other status information. Common fields include:  A set of bits  Condition Codes  Sign of last result  Zero  Carry  Equal  Overflow  Interrupt enable/disable  Supervisor

3  The CPU consists of several sections and it must do the following: › Fetch instructions: The CPU reads an instruction from the memory. › Interpret instructions: Decoding determines what action will be taken. › Fetch data: Sends a control signal to and receives control signals from other devices. › Process data: Where an instruction may need performing arithmetic or logical operation on the data. › Write data: Depending on the performance it may require writing data to memory or an I/O module.  A CPU is known to carry out instructions and makes the rest of the computer carry out their task.



6  A register is a small amount of available storage on the CPU where it can be reached quickly.  They are special memory used by the CPU for temporarily storing data during execution of instruction.  Number and function vary between processor designs among registers.  Registers are measured by the number of bits they can hold, for example, we call a register holding 8 bits an 8 bit register.  Registers have top level of memory hierarchy.

7  User Visible Registers are those that can be referenced by the machine language that the processor executes.  They enable the machine to minimize main memory references by modifying the use of registers.  General Purpose: can be assigned to a variety of functions.  Data: used to hold data and cannot be employed in the calculation of an operand address.  Address: can be general purpose or can be for one particular addressing mode.  Condition Codes: also called flags, they are bits set by the processor hardware due to the operations.

8 In order to control the operation of the processor, there are a few registers that are to be used.  Program Counter(PC): PC contains the action that will be fetched either the address of the instruction being executed, or the address of the next instruction to be executed.  Instruction Register(IR): It contains the instruction currently being executed.  Memory Address Register(MAR): Contains the address of a location in memory.  Memory Buffer Register(MBR): It stores the data being transferred to and from the immediate access store.


10 An instruction cycle is the sequence of actions that the CPU performs to execute each machine code instruction in a program.

11  Fetch: Read the next instruction from memory to processor.  Execute: Interpret the opcode and perform the indicated operation. May take many forms; it depends on instruction being executed. May include: Memory read/write Input/Output Register transfers ALU operations  Interrupt: If enabled and it has occurred, save process state and service the interrupt.

12  The execution of an instruction may involve one or more operant in memory, each of which requires memory access  Indirect addressing is used, then additional memory accesses are required.  Can be thought of as additional instruction subcycle



15 Fetch Cycle Indirect Cycle Interrupt Cycle




19  It’s a technique used in microprocessors to speed up the execution of a program by reducing wait states.  Prefetching occurs when a processor requests an instruction from main memory before it is actually needed. Once the instruction comes back from memory, it is placed in a cache. When an instruction is actually needed, the instruction can be accessed much more quickly from the cache than if it had to make a request from memory.  Since programs are generally executed sequentially, performance is likely to be best when instructions are prefetched in program order.


21  An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase the instructions that can be executed in a unit of time.

22  Fetch instruction  Decode instruction  Calculate operands (i.e. EAs)  Fetch operands  Execute instructions  Write result  Overlap these operations


24  A branch (or jump on some computer architectures, such as the PDP-8 and Intel x86) is a point in a computer program where the flow of control is altered.  The term branch is usually used when referring to a program written in machine code or assembly language.  In a high-level programming language, branches usually take the form of conditional statements, subroutine calls or GOTO statements.



27  Multiple Streams  Prefetch Branch Target  Loop buffer  Branch prediction  Delayed branching

28  Have two pipelines  Prefetch each branch into a separate pipeline  Use appropriate pipeline  Leads to bus & register contention  Multiple branches lead to further pipelines being needed

29  Target of branch is prefetched in addition to instructions following branch  Keep target until branch is executed  Used by IBM 360/91

30  Very fast memory  Maintained by fetch stage of pipeline  Check buffer before fetching from memory  Very good for small loops or jumps  c.f. cache  Used by CRAY-1


32  Predict never taken › Assume that jump will not happen › Always fetch next instruction › 68020 & VAX 11/780 › VAX will not prefetch after branch if a page fault would result (O/S v CPU design)  Predict always taken › Assume that jump will happen › Always fetch target instruction

33  Predict by Opcode › Some instructions are more likely to result in a jump than thers › Can get up to 75% success  Taken/Not taken switch › Based on previous history › Good for loops

34  Delayed Branch › Do not take jump until you have to › Rearrange instructions



37  Fetch › From cache or external memory › Put in one of two 16-byte prefetch buffers › Fill buffer with new data as soon as old data consumed › Average 5 instructions fetched per load › Independent of other stages to keep buffers full  Decode stage 1 › Opcode & address-mode info › At most first 3 bytes of instruction › Can direct D2 stage to get rest of instruction  Decode stage 2 › Expand opcode into control signals › Computation of complex address modes  Execute › ALU operations, cache access, register update  Writeback › Update registers & flags › Results sent to cache & bus interface write buffers


39 1. What is a small amount of available storage on the CPU where it can be reached quickly? 2. What must the CPU do? 3. Does a memory buffer register store data being transferred to and from the immediate access store 4. What is an instruction cycle? 5. Is additional memory access required if indirect cycles are used? 6. What is prefetching? 7. What is a pipeline? 8. What is a branch? 9. Can unconditional branches be ignored? 10. What is loop buffer used for?

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