Instructor: Oluwayomi Adamo Digital Systems Design

 Combinational Circuit Design Using VHDL  Demo – Full Adder  Hands-On Exercise – Combinational Circuit

 Combinational Circuit – Output of the circuit depends solely on the current inputs.  No memory and implemented using conventional logic gates. Combinational Logic outin Storage element Combinational Logic Present state Next state inout Sequential logic Combinational logic

Basic Gates

 L(A1,A0,B1,B0) = A1’B1 + A0’ B1 B0 +A1’ A0’B0 A1A0 B1B

 Static 1-hazard – If output must be 1, but momentarily goes to 0 for some change in inputs and some combination of propagation delays  Static 0-hazard – If output must be 0, but momentarily goes to 1 for some change in inputs and some combination of propagation delays

What happens when a changes from 1 to 0? A=0, but A’ does not become 1 until the inverter delay has passed. (a) (b)

 VHDL is inherently concurrent (Parallel)  Only statement inside a process, function, or procedure are sequential  Combinatorial circuit are built with concurrent code.  Concurrent statement in VHDL are WHEN and GENERATE.

 When  WHEN ='1' ELSE  ;  With sel select  with HEX SELect  LED<= "1101" when "00",  "0100" when “01",  "0000" when “10",  "1001" when “11",  "0010" when others;

 Full Adder (structural model from half adder)  4-bit Adder (using structural model from full adder)  2-1 Multiplexer  4-1 Multiplexer (using structural model) Design, Simulate and Implement each of this units. Assignment: Generate a truth table and use K- Map to realize a simplified equation for full adder, 2-1 multiplexer.

 Good Luck!!!