1. Special Gates Combinational Logic Gates
Lecture 2

2. invert inputs and output.
DeMorgan's Law
Converting AND to OR (with some help from NOT)
Consider the following gate:
To convert AND to OR
(or vice versa),
invert inputs and output. A B 1
If there's time, perhaps discuss how all gates can be implemented with NAND (or NOR).
Therefore, you can implement any truth table using only NAND (or NOR) gates.
Same as A+B!

3. More than 2 Inputs? AND/OR can take any number of inputs.
AND = 1 if all inputs are 1.
OR = 1 if any input is 1.
Similar for NAND/NOR.
Can implement with multiple two-input gates, or with single CMOS circuit.
NAND and NOR are not associative.
Jim Conrad’s example:
NAND(NAND(0,0), 1) = NAND(1, 1) = 0
NAND(0, NAND(0,1)) = NAND(0, 0) = 1

16. Half adder The sum is XOR operation and the carry an AND: A B S C 1 C1
Jess 2006

17. Examples The half adder A B S C 1
The half adder is a circuit for adding two single bit numbers
Develop a truth table and Boolean expressions for the half adder A B S C 1
carry 1
A B S C
s = notA.B + BnotA
= A + B
c = A.B
S and C are the Sum and Carry
Jess 2006

18. Examples The full adder
Develop a truth table and Boolean expressions for the full adder, this circuit also includes a carry in.
Cin A B S C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Sum A
full
adder B
carry 1
Cout
Cin
0Cin1 0Cin1 1Cin1 1Cin1
1 0carry1 0carry1 1carry 1
SUM
Cin AB 00 01 11 10 1 1
Cin A B S C
Jess 2006 1 1 1
Cout
A BC 00 01 11 10 1 1 1 1 1

19. Truth table for full adder
C in A B S
C out 1
Exercise:
Complete the Karnaugh maps for the Sum and the Carry out columns
Jess 2006

20. K maps for sum and carry AB C in 00 01 11 10 1 AB C in 00 01 11 10 1
Sum – 1 when odd number of inputs is 1 = XOR gate
Carry out - simplifies to 3 pairs AB
C in 00 01 11 10 1 AB
C in 00 01 11 10 1
C out = A.B + A.Cin + B.Cin
Sum = Cin xor A xor B
Jess 2006

21. Full adder circuit A B Sum Count C in Sum = Cin xor A xor B
Cout = A.B + A.Cin + B.Cin
Jess 2006

22. Examples The Multiplexer
Selects one of 2n inputs and copies it to a single output
The selected line is determined from the bit combination (address) on the n selection lines
e.g. 1 from 2 mutiplexer
n = 1 a
out b 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
sel a b out
sel
sel a b out
A BC 00 01 11 10
sel ab 00 01 11 10 1 1 1 1 1 1
out = not(sel).a + sel.b
out =
Jess 2006

23. 2:1 Multiplexer sel a b out ? 1 sel a b out 1 AB sel 00 01 11 10 1? 1
sel a b
out 1
if a is selected, don’t care about b. AB
sel 00 01 11 10 1
Jess 2006

24. K map for 2:1 Multiplexer AB sel 00 01 11 10 1 output = sel.a + sel.b1
output = sel.a + sel.b
data
Principal can be extended to
4:1 – 2 select lines and 4 data lines
8:1 – 3 select lines and 8 data lines
and so on…
out
sel
Jess 2006

25. What you should be able to do:
Change circuits using one set of gates (eg AND, OR, NOT) to their equivalent using NAND or NOR gates only (and vice versa).
Be familiar with half-, full- adders and multiplexer circuits.
Be able to construct and interpret Karnaugh maps with up to 4 input variables.
Jess 2006