Electronics for Si-W calorimeter LCWS06 Bangalore – March, 10 th Gérard Bohner, Pascal Gay, Jacques Lecoq Samuel Manen, Laurent Royer Michel Bouchel, Bernard Bouquet, Julien Fleury Christophe de La Taille, Gisèle Martin, Roman Poeschl

General introduction

General overview of Si-W calo CALICE ECAL proposal (LDC) : Octogonal shape 40 identical structures Active materials in detector slab Million channels Depending on pad size (1cm or.5cm) Electronic requirement : Electronic embedded in the slab Ultra-low power consumption (~100µW/Ch) To avoid active cooling Ultra-thin design To reduce moliere radius R&D on a technologic prototype as started

EUDET framework European funding for ILC detectors CALICE labs are members of JRA3 (Joint Reasearch Activities for calorimeters) Part of this funding will be used to build a technologic prototype of ECAL EUDET is a 4-year funding program  Technologic prototype is a 2009 deliverable That technologic prototype has to be as close as possible to final design

EUDET : ECAL emodule Electromagnetic calorimeter technologic prototype Prototype of a (~ 1/6) module 0 : one line & one column 150 cm long, 12 cm wide 30 layers channels Test full scale mechanics + PCB Can go in test beam Test full integration + edge communications Similar in #channels as physics prototype ©M. Anduze (LLR)

R&D on PCBs

Thickness considerations Chip in the detector Thickness Ultra-thin PCB Chip burried in PCB FE chip (1mm)Wafer (500µm)PCB (600µm) 1750µm diodes+ FE electronic

Length considerations Industry can’t build 1.5m PCB Stitchable PCBs (no room for cables) Feasability prototypes in fab PCB type 1PCB type 2PCB type 3 Glue ? Solder ? 1.5m

Front-end chip R&D

Requirements for FEE Ultra-low dissipation (100µW/ch) involves : Self-triggered ASIC : Zero-suppress on the chip On chip A/D conversion and memory to buffer outputed data Ultra-thin design involves : Stand-alone ASIC : no room for decoupling capacitance Huge number of channels involves : System on Chip : all features have to be integrated Calibration, ADC, analogue memory, digital memory, BCID, back- end bus, etc.  Chip output : digital formated data

Power comsumption & integration The critical issue : power consumption ATLAS FEB 1W/Ch 400*500mm FLC physic proto 5mW/Ch 10*10mm ILC 100µW/Ch 2010

Power flexing : pulsed electronic time Time between two trains: 200ms (5 Hz) Time between two bunch crossing: 337 ns Train length 2820 bunch X (950 us) Acquisition 1ms (.5%) A/D conv..5ms (.25%) DAQ.5ms (.25%) 1% duty cycle IDLE MODE 99% duty cycle 199ms (99%)  See ILC_PHY4 results Based on TESLA TDR

On chip formated data ADC result - 12 bit BCID – 12 bit Gain - 2 bit Channel nb - 6 bit Chip ID - x bit PositionEnergyTime  32bits / event without Chip ID

Data rates Assuming TESLA like bunch structure Bunch crossing period within bunch train = 176ns ~ 200ns Number of crossings per bunch train = 4886 ~ 5000 Bunch train length = 860µs ~ 1ms Bunch train period =250ms ~ 200ms Raw Data volume 2 bytes Energy data/Channel, 20 Million channels Raw data per bunch train ~ 20M  5000  2 ~ 200GBytes ECAL No way to digitize inside the ~ ms train 10 kbytes/channel/train ~ 50 kbytes/ch/s Physics data rate : 90 Mbytes/train = ~20 bytes/ch/s Zero suppression mandatory 10 3 rate reduction -> drastic for power dissipation Digitize only signals over 1/2MIP with noise < MIP/10 Allow storage in front-end ASIC

R&D building blocks

High dynamic range structure Low noise charge preamp 3 integration shaper (G. 2, 20 & 100)

Functionaality test SimulationMeasurement (Oscilloscope) Gain 2 Gain 20 Gain 100

Linearity measurement Gain 2 : NL 4 ‰ Gain 100 : NL 7 ‰ Gain 20 : NL 4 ‰

Pipeline ADC Vin b1b2b3b4b5b6b7b10 b9 b8 10 bits ADC → 10 stages Comparator V ref V IN Amplifier Gain=2 V ref Gnd Bit N out To V IN stage N+1 Stage N of pipeline ADC block schema

Pipeline ADC measurement  Gain : instead of 2  Offset : 18mV (cumulated)  1.5 bit/stage correction  integral non linearity ±2 LSB

ILC_PHY4 : a first step toward final ASIC 18 channels Multi gain charge preamp (167mV/pC  2.5V/pC) Dual shaper gain 1&10 2 track and hold Switchable calibration injection capacitance 2 analogue multiplexers 18  1 One for gain 1 and one for gain 10 The two MUX output are MUX to a single output 1 ADC – 12 bit / 1MSPS – IP from AMS (founder) An internal bias device including : Internal decoupling on current sources Idle mode on whole analogue parts of the chip

ILC_PHY4 layout & status -Chip produced & packaged -Test board produced - Missing test board firmware  Ready before summer Test to be performed April/May bits ADC IP

Power pulsing on ILC_PHY4 Tested on a stand-alone preamp Switching from idle current (i/1000) to nominal On-setting time < 20 µs Pulse amplitude and noise identical in pulsed mode than in steady mode Allows to reduce power by 99% with beams 2ms/200ms Target power of 100 µW/channel appears within reach : to be validated in testbeam in 2006 with ILC_PHY4 ASIC ON signal Ready for pulse RFCFRFCF 20 µs Log scales !

Schedule Multi channel prototype foundry planned in spring06 including : Analogue front-end Power pulsed Self-biased Self-trigger Pipeline ADC (LPCC) Stitchable PCB planned for october06

Conclusions CALICE collaboration help by EUDET (european funding) will built a technological prototype as close as possible to the final detector. That technological prototype will validate the feasibility of the full detector Many ASIC R&D are performed to have all the building blocks before the end of the year Thin stitchible PCBs are currently in design.

Spare slides

Test plans

Front-end ASIC in a EM shower Summer with FLC_PHY3 + FEV3

A/D conversion on chip ILC_PHY4 test to check mixed chip performance New foundry LPC+LAL with LPC 12-bit pipeline ADC