July 10, th VLSI Design and Test Symposium1 BIST / Test-Decompressor Design using Combinational Test Spectrum Nitin Yogi Vishwani D. Agrawal Auburn University, Dept. of Elec. & Comp. Eng. Auburn, AL 36849, U.S.A. 13th IEEE / VSI VLSI Design and Test Symposium Bangalore, India

July 10, th VLSI Design and Test Symposium2 Outline  Problem Definition  Proposed Design Method Spectral Analysis BIST Architecture  Results Results without reseeding Results with reseeding  Conclusion

July 10, th VLSI Design and Test Symposium3 Problem Definition  To design a Test Pattern Generator (TPG) for Built-In Self Test (BIST) of combinational circuits achieving the following goals: Given a set of pre-generated test vectors, replicate their effects in hardware Low area overhead Low test application times

July 10, th VLSI Design and Test Symposium4 Proposed Design Methodology Determine prominent spectral components by spectral analysis Preprocess test vectors Pre-generated test vectors BIST implementation Step 1 Step 2 Spectral properties BIST TPG gate-level netlist

July 10, th VLSI Design and Test Symposium5 Walsh Functions and Hadamard Matrix H(3) = Walsh functions: a complete orthogonal set of basis functions that can represent any arbitrary bit- stream. Walsh functions form the rows of a Hadamard matrix. Example of Hadamard matrix of order w0w0 w1w1 w2w2 w3w3 w4w4 w5w5 w6w6 w7w7 Walsh functions (order 3) time

July 10, th VLSI Design and Test Symposium6 Test Vectors and Bit-streams Circuit Under Test (CUT) Input 1 Input 2 Input 3 Input 4 Input 5 Input J Vector 1 → Vector 2 → Vector 3 → Vector 4 → Vector 5 → Vector K → Outputs Time A binary bit-stream to be spectrally analyzed

July 10, th VLSI Design and Test Symposium7 Spectrum: Input 1 of circuit s5378 Spectrum of ATPG bit-stream applied to input 1 of circuit s5378 Theoretical random noise level (16)

July 10, th VLSI Design and Test Symposium8 Spectrum: Input 9 of circuit s5378 Spectrum of ATPG bit-stream applied to input 9 of circuit s5378 Theoretical random noise level (16)

July 10, th VLSI Design and Test Symposium9 Effect of Noise  Noise inserted in ATPG vectors, generated for a sample of faults (RTL faults), for s5378 circuit, using increasing spectral threshold (ST) values (i.e., increasing noise)  226 ATPG vectors for1602 RTL faults Gate-level faults detected by 226 ATPG vectors More faults detected than original vectors

July 10, th VLSI Design and Test Symposium10 To CUT BIST Architecture Weighted pseudo- random pattern generator Spectral component synthesizer Input 1 Input 2 Input 3 Hadamard Components To CUT Randomizer Hadamard wave generator System clock BIST clock Weighted pseudo-random bit-streams N-bit counter with XOR gates SC 1 SC 2 SC 3 Weighted random bit-stream (W=0.5) Proportion: SC 1 = 0.5 SC 2 = 0.5 Proportion: SC 1 = 0.25 SC 2 = 0.25 SC 3 = 0.5 Cellular Automata Register with AND-OR gates System clock BIST clock Weighted random bit-stream (W = 0.25) Bit-stream of spectral component Noise inserted bit-stream

July 10, th VLSI Design and Test Symposium11 3-bit down counter; N flip-flops For H(N) Hadamard Wave Generator FF 1 FF 2 Logic ‘1’ FF 3 W0W0 W1W1 W2W2 W3W3 W 4 W5W5 W6W6 W7W7 LSB MSB CLK C. K. Yuen, “New Walsh-Function Generator,” Electronics Letters, vol. 7, p. 605, 1971.

July 10, th VLSI Design and Test Symposium12 Generation of Weighted Random Bit-streams Cellular Automata Register M Flip-flops P1=0.5 P1=0.25 P1=0.5 P1=0.625 P1=0.5 P1=0.75 P1=0.875 P1= CircuitNo. of PI No. of Flip-flops Hadamard wave gen. (N)CA register (M) c s15850 (comb.)600728

July 10, th VLSI Design and Test Symposium13 Spectral BIST Results and Area Overhead Circuit Random vectors Weighted Random vectors Spectral BIST ATPG Coverage (No. of vecs) c %97.86%99.81%100% (247) s15850 (combinational) 96.81%97.41%98.77%100% (530) Test coverage results without reseeding (64000 vectors) Circuit No. of gates in circuit Spectral BISTPRPG No. of gates % Area overhead No. of gates % Area overhead c s15850 (combinational) Area overhead comparison

July 10, th VLSI Design and Test Symposium14 Test Coverage vs Number of Vectors

July 10, th VLSI Design and Test Symposium15 Test Coverage vs Number of Vectors

July 10, th VLSI Design and Test Symposium16 Reseeding of Spectral TPG To CUT Data from external tester Serial scan interface Parallel interface Spectral BIST / Decompressor Flip-flops BIST / Decompressor Logic Mode of operationFunction External Tester Mode (ETM)One-seed-per-test vector operation Hybrid BIST Mode (HBM)Used to generate test vectors and reseed flip-flops periodically

July 10, th VLSI Design and Test Symposium17 Spectral TPG Results with Reseeding Mode of test application No. of vecs./ seeds No. of inputs Test data volume (bits) No. of tester cycles No. of system clock cycles Test time (us)† Conventional (parallel) Conventional (serial) Spectral BIST ETM (parallel) ETM (serial) HBM (parallel) HBM (serial) Comparison of test data volume and test time for c7552 † assuming tester clock period T tester =10ns and on-chip system clock period T clk =1ns

July 10, th VLSI Design and Test Symposium18 Spectral TPG Results with Reseeding Mode of test application No. of vecs./ seeds No. of inputs Test data volume (bits) No. of tester cycles No. of system clock cycles Test time (us)† Conventional (parallel) Conventional (serial) Spectral BIST ETM (parallel) ETM (serial) HBM (parallel) HBM (serial) Comparison of test data volume and test time for s15850 (combinational) † assuming tester clock period T tester =10ns and on-chip system clock period T clk =1ns

July 10, th VLSI Design and Test Symposium19 Conclusion  Proposed a TPG design methodology for combinational circuits using spectral techniques. Also proposed a reshuffling algorithm to enhance spectral components.  Designed TPG exhibits the following: Higher test coverage than random and weighted random vectors for equal number of test vectors. Encouraging test data compression capabilities up to 95%. An order of magnitude reduction in test application time.  Issues to address: Slightly high area overhead  Overhead might reduce by:  Implementation on larger circuits  Optimum selection of spectral components by reshuffling algorithm Increase in test time for parallel HBM  Optimum seeds and intervals for reseeding can reduce the test time.

July 10, th VLSI Design and Test Symposium20 Thank you. Questions please?

July 10, th VLSI Design and Test Symposium21 Pre-processing of Test Vectors Reshuffling Algorithm: Input Data and Parameters: N I : No of inputs N V : No. of vectors V(1:N V,1:N I ): Test vector Set of dimensions N V x N I hd: Dimension of Hadamard matrix H: Hadamard transform matrix of dimension 2 hd x 2 hd Procedure: Vector set V appended with redundant vectors to make weighting of bit-streams of all inputs = 0.5 for i=1 to N I Perform spectral analysis on bit-stream of input i: S = V(:,i) x H; Pick the prominent spectral component Sp(i) from S Rearrange vector set V such that maximum bits in the bit-streams of inputs 1 to i match with the picked prominent spectral components Sp(1 to i) respectively. end