Overview of TPC Front-end electronics I.Konorov Outline:  TPC prototype development  Readout scheme of the final TPC detector and further developments  Conclusions

April Grünberg PANDA FEE-DAQ workshop Igor Konorov

Signal detection and Time/Amplitude measurements April Grünberg PANDA FEE-DAQ workshop Igor Konorov Threshold RO architecture: Signal sampling –Amplitude : Maximum –Time extraction Amplitude Ratio Digital CFD PreAmpShaperAnalog Sampling MUX

TPC prototype April Grünberg PANDA FEE-DAQ workshop Igor Konorov Geometry : 10.5 cm inner diameter 30 cm outer diameter 73 cm drift distance ReadOut : channels 511 samples More than 5 10^6 space points

AFTER ASIC 90 ns peaking time Analogue Sampling(SCA),10-20MHz 511 Samples/Channel No Zero Suppression 72(64) channels/chip Very slow sequential readout –1-2 ms/event 600 eˉ ENC with detector Objectives: TPC characterization Optimization feature extraction algorithms FOPI real data taking April Grünberg PANDA FEE-DAQ workshop Igor Konorov PreAmpShaperAnalog Sampling MUX

Readout chain April Grünberg PANDA FEE-DAQ workshop Igor Konorov 42 AFTER FE cards 11 ADC 2 HGESiCA PCI card in PC (event building)

April Grünberg PANDA FEE-DAQ workshop Igor Konorov

April Grünberg PANDA FEE-DAQ workshop Igor Konorov

RO status Complete detector equipped with RO electronics Noise performance is about 600e- Stable data taking during last test Hz trigger rate(2.5 ms dead time) Maximum 2.5% occupancy (0.5 MB/ev) Everything is ready for FOPI run in June April Grünberg PANDA FEE-DAQ workshop Igor Konorov

Problems with commissioning large detector Power distributions Grounding Optical links Temperature Sensors Revision of detector design at early stage to be foreseen April Grünberg PANDA FEE-DAQ workshop Igor Konorov

Towards final PANDA TPC detector April Grünberg PANDA FEE-DAQ workshop Igor Konorov

GEM TPC requirements About 80K channels with hexagonal pads of 5.8 mm² eˉ ENC 4 ns signal time resolution to determine Z coordinate 8 bit amplitude resolution for dE/dX measurements Continuous readout 200 kHz hit 10  April Grünberg PANDA FEE-DAQ workshop Igor Konorov

Design challenges Low noise in mixed Analog/Digital environment Signal processing – feature extraction High data rate Relatively High channel density Cooling April Grünberg PANDA FEE-DAQ workshop Igor Konorov

Considered ASICs for final TPC 1.XYTER – CBM –CSA => Discriminator TDC => Peak Sensitive ADC 2.S-ALTRO – ILC – CSA=> Sampling ADC => Zero suppression 3.PCA16 + Transient Recorder – PANDA –CSA=> Analogue Sampling => Zero Suppression 4.SPADIC – CBM TRD –CSA=> Sampling ADC => Zero suppression April Grünberg PANDA FEE-DAQ workshop Igor Konorov

Transient Recorder ASIC Status First prototype to be submitted in Spring 4 channels No zero suppression Goal of prototype Testing SCA(Switched Capacitor Array) performance April Grünberg PANDA FEE-DAQ workshop Igor Konorov

SPADIC: Self triggered Pulse Amplification and Digitization asIC April Grünberg PANDA FEE-DAQ workshop Igor Konorov

SPADIC ASIC Status of Latest Prototype (SPADIC v0.3) ● 8 complete channels (plus 18 test channels) ● Positive input charges, about 0..40fC input range ● 2nd order shaping, 90 ns shaping time ● Noise: 30 pF capacitive input load ● ADC with 7.5 Bit effective 25 Msamples/s ● Power per Channel/ADC: 3.8/4.5 mW ● Size: 1.5 x 3.2 mm2 Status of Latest Setup ● 8 complete setups have been CERN Testbeam Nov ● New PCB with low noise layout and reduced ground loops has just been designed and is now being fabricated ● Ongoing software development (config. + monitoring tools) First full-blown SPADIC (v1.0) ● Design phase has just been started ● Planned Submission: summer/fall 2011 ● First measurement results end of 2011 at the earliest April Grünberg PANDA FEE-DAQ workshop Igor Konorov

ASICs summary table April Grünberg PANDA FEE-DAQ workshop Igor Konorov XYTERS-ALTROPCA16+TRSPADIC # channels12816/6432 Peaking Time(ns) 20, Sampling-20 MHz MHz25 MHz Power24 mW/ch16 mW/ch~10 mW/ch~12 mW/ch Availability /? Power Cons. 80 kCh. 1.9 kW1.2 kW0.8 kW1.0 kW

Next steps Development of FE prototype using PCA16 and commercial ADC or ALTRO chip 100 PCA16 chips purchased – 1600 channels Commercial ADC MHz, ALTRO Digital logic in FPGA Goal: –Study system integration Powering scheme Noise optimization of mixed Analog/Digital system –Develop Cooling system concept –Solid number for material budget –Detector test with fully functional prototype April Grünberg PANDA FEE-DAQ workshop Igor Konorov

Data rate and data processing 320 FE cards, 80 GB/s Zero suppression 10 Data Concentrators, 50 GB/s Feature extraction TPC SuperBurst Building Network 25 GB/s Clustering Full Suberburst Building Network 200 GB/s Compute Nodes Further data reduction April Grünberg PANDA FEE-DAQ workshop Igor Konorov Data Structure Data organized in Super Bursts of 500 μs Last 50 us of data copied to next block to resolve boundary effects SODA Front End Cards Data Concentrator Building Network Compute Node SODA

Readout chain and responsibilities Detector group responsibility DAQ group responsibility April Grünberg PANDA FEE-DAQ workshop Igor Konorov SODA Front End Cards Data Concentrator Building Network Compute Node SODA

TPC Data concentrator April Grünberg PANDA FEE-DAQ workshop Igor Konorov Features: uTCA/AMC card Lattice FPGA ECP3 4(2) GB DDRAM Configurations: 2x7x1 Concentrator 8x8 Switch

ATC module April Grünberg PANDA FEE-DAQ workshop Igor Konorov 32 x 32 switch, 10 GB/s bandwidth

Conclusions GEM TPC readout concept, based on AFTER ASIC provided and allow to do full TPC characterization Few ASIC chips being developed and some of them will be available for final detector Developing next FE prototype with data driven readout based on PCA16+Commercial ADC is planned Data concentrator board being developed April Grünberg PANDA FEE-DAQ workshop Igor Konorov

BACKUP SLIDES April Grünberg PANDA FEE-DAQ workshop Igor Konorov

SUPER ALTRO CERN’s ASIC for ILC TPC –12 bits –20 MSPS –16/64 channels/chip –Expected power consumption –16 channel version was submitted, very limited number of chips –64 channel version no plans yet 16/64 channels/chip, CMOS µm April Grünberg

Transient Recorder April Grünberg PANDA FEE-DAQ workshop Igor Konorov 180 nm 32 channels/chip 4.5x4.5 mm²