25 Sept 2001Tullio Grassi From MAPLD2001 ( space community conference ) Major causes of failures

25 Sept 2001Tullio Grassi From MAPLD2001 ( space community conference ) Major causes of failures Lack of design audit Lack of monitoring for young designers Management consider engineers plug-compatible

25 Sept 2001Tullio Grassi HCAL TRIDAS electronics Tullio Grassi Univ. of Maryland CMS week - HCAL meeting Sept 2001 In Collaboration with Boston University, Fermilab, Princeton University, University of Illinois

25 Sept 2001Tullio Grassi HCAL FE/DAQ Overview Shield Wall CPUCPU DAQ RUI HPD FE MODULE DAQ DATA SLINK64 [1 Gbit/s]  18 HTRs per Readout Crate FRONT-END RBX Readout Box (On detector) READ-OUT Crate (in UXA) Trigger Primitives Fibers at 1.6 Gb/s 3 QIE-channels per fiber QIE CCA GOL DCCDCC TTC GOL CCA HTRHTR HTRHTR HTRHTR CAL REGIONAL TRIGGER MHz MHz CCA

25 Sept 2001Tullio Grassi Trigger Tower to Readout Crate Mapping for the HCAL Assumptions: One HCAL depth in barrel and endcap regions Optical link at 80 MHz with 3 HCAL channels per fiber Each TT is formed from 1 to 7 depths. Preliminary mapping available on:

25 Sept 2001Tullio Grassi Readout - 9U VME crate 20 m Copper Links 1 Gb/s DAQ Calorimeter Regional Trigger HRCHRC HRC (HCAL Readout Control) card CPU for slow monitoring Fanout of timing signals Central JTAG controller HTR ( HCAL Trigger and Readout ) cards FE-Fiber input Trigger Primitives output to CRT DAQ/TP Data output to DCC Spy Out DCC (Data Concentrator Card) card Input from HTRs Output to DAQ Spy Out Gbit 1.6 Gb/s FanOutFanOut HTRHTR Front End Electronics HTRHTR DCCDCC HTRHTR HTRHTR... 2 nd D C ?

25 Sept 2001Tullio Grassi HTR board- present scheme DAQ-data to DCC Timing Input (TTC, etc) FE data Inputs: 8 FE fibers 24 QIE-channels Trigger Primitive outputs 1 Gb/s copper link 24 Trigger Towers OPTICAL RX DESER... DESER P2 Ser. LVDS TX VME Interface & Config. (FPGA) SLB -PMC (ECAL design) FPGA Trigger Path DAQ Path 8 Trig Towers SLB -PMC (ECAL design) SLB -PMC (ECAL design) Spy Output (VME) P1

25 Sept 2001Tullio Grassi “Denser” HTR Strong demand for a denser scheme. GOAL: 16 FE-fibers (25 Gb/s)  48 Trigger Tower/HTR ‘Bottleneck’ is the number of SLBs (=Trigger output) and their size. The size is related to the Trigger Link technology The number is related to: 1 FE-channel  1 TrigTower NB: a denser design requires 2 links to DCC.

25 Sept 2001Tullio Grassi Front-panel space on 9U boards = (holes subtracted) 8-fiber option 3 SLB-PMC……………. 15 cm 2 Quad opt. Rx…………. 5 cm DAQ output….………… 1.2cm Timing inputs…………… 2 cm Sub-total...…… 23.2cm LEDs…………………… 2.5cm switch, button, spares... 3 cm 5% contingency……… 1.5 cm Total……… cm 12-fiber option 5 SLB-PMC……………. 25 cm 1 Parallel opt. Rx………. 2 cm DAQ output.…………… 1.2cm Timing inputs…………… 2 cm Sub-total...…… 30.2cm LEDs…………………… 2.5cm switch, button, spares... 3 cm 5% contingency……… 1.5 cm Total……… cm 32.5 cm 8 fibers/ 24 QIE channels Vs 12 fibers/ 36 QIE channels New ideas needed here ! From June 2001 presentation

25 Sept 2001Tullio Grassi ‘Double HTR’- 1st Scheme OPTICAL RX DES P1 P2 LVDS TX SLB -PMC (ECAL design) FPGA Trigger Path DAQ Path SLB -PMC (ECAL design) SLB -PMC (ECAL design) SLB -PMC (ECAL design) SLB -PMC (ECAL design) DES FPGA Trigger Path DAQ Path DES LVDS TX OPTICAL RX Board and Front-Panel very dense SLB -PMC (ECAL design) Thin cables & connectors (airflow ?) Thick cables & connectors (Trigger specs)

25 Sept 2001Tullio Grassi 366 mm SLB -PMC (ECAL design) 29 mm Thick cables & connectors (Trig. specs) Thin cables & connectors (airflow ?) Board and Front-Panel very dense ‘Double HTR’- 1st Scheme

25 Sept 2001Tullio Grassi ‘Double HTR’- 2nd Scheme OPTICAL RX DES P1 P2 LVDS TX SLB -PMC (ECAL design) FPGA Trigger Path DAQ Path SLB -PMC (ECAL design) SLB -PMC (ECAL design) SLB -PMC (ECAL design) SLB -PMC (ECAL design) SLB -PMC (ECAL design) DES FPGA Trigger Path DAQ Path DES LVDS TX OPTICAL RX Thin cables & connectors Thick cables & connectors (Trigger specs) Mechanical problems (board extraction)

25 Sept 2001Tullio Grassi ‘Double HTR’- 3rd scheme OPTICAL RX DES P1 FPGA Trigger Path DAQ Path DES FPGA Trigger Path DAQ Path DES OPTICAL RX P2 48 TPs LVDS TX Transition Board SLB -PMC (ECAL design) SLB -PMC (ECAL design) SLB -PMC (ECAL design) SLB -PMC (ECAL design) SLB -PMC (ECAL design) SLB -PMC (ECAL design) Throughput ~17 Gb/s SER/DESER+resync Latency: + 2 T CK 9U board “easy” Custom ?

25 Sept 2001Tullio Grassi TTC Fanout board First prototype design finished Rx_BC0 LVDS Fanout Rx_CLK LVDS Fanout TTCrx Adapter Card (testing) Rx_BC0 Rx_CLK TTC LVDS TTC PECL Decoder FPGA TTCrx Chip TTC LVDS Fanout TTC LVDS Optical Receiver PECL / LVDS

25 Sept 2001Tullio Grassi TTC Fanout board First prototype layout P1/J1 P2/J2 Optical Receiver AMP Modular Jack Connector (x8) (x4) 20 RJ-45 connectors on the front panel Category 5e cable to transmit LVDS. Each cable will transmit 3 differential pairs: TTC, RX_BC0 and RX_CLK. On HTRs, only one RJ-45 connecter is needed to receive the three LVDS signals.

25 Sept 2001Tullio Grassi Considerations on TTCrx Chip Tiny adapter card TTCrx chip 3cm (1400mil) PLCC 84-PIN Layout for TTCrx Adapter Card Samtec Low Profile Headers are used as connectors for the adapter card to achieve high performance. Receiving LVDS differential inputs. Termination and AC- couple are implemented on the adapter card for high performance. 100mil

25 Sept 2001Tullio Grassi Status Gained experience with links Overlapping tasks: Demo + Proto = Hard time Started the design for HTR-prototype Problems for optical receivers “Pre-prototype” being submitted this week

25 Sept 2001Tullio Grassi Demonstrator Requirements Resources Links 6U board Prototype Estimated full channel count Simple Algorithms Pre-Prod Study Corner cases and HF Production Test bench Slice Test I Project Timeline FNAL source calib. Cern Test Beam 2004 Slice Test II Pre-prod too short: not useful Test bench before production ? Slice Test I with pre-production ?

25 Sept 2001Tullio Grassi 2002 Test Beam Lesson from Source Calibration: Simple is better Simplified algorithms in HTR: baseline HTR or ‘double HTR’ raw data in QIE format ? Zero suppression or all data ? BCID No trigger output Unlikely to have a real prototype with all the feature of the final system (elaborated data processing, Trigger Primitives, Design for Testability, Central configuration, etc).

25 Sept 2001Tullio Grassi 2002 Test Beam Help from FNAL: FEE module to test HTR TTC fanout board (from Weiming) DCC needs event builder Slink32 transmission to a CPU Test Beam experience  Pre-production (end of 2002)