1. CMS/CERN. Nov, 2001HCAL TriDAS1 HCAL Fiber Link Issues Use of CMS Tracker Fiber Links Drew Baden University of Maryland John Elias Fermilab

2. CMS/CERN. Nov, 2001HCAL TriDAS2 Constraints Front End –Each Readout Module (RM) has 3 QIE boards of 2 fibers each Total of 6 fibers per RM –Each RBX has 4 RMs Total of 24 fibers per RBX, 72 channels total (3 channels per fiber) –Magic Number: 3 and 6 TPG output –Each SLB sends 4 twisted pair to regional trigger Each pair has 2 TPG towers = 8 TPG per SLB –Magic Number: 8 So, HTR is in the middle of all of this! –3 x 8 = 24 channels ideal Would required 3 SLBs but 6 will fit on backplane Each of 2 FPGAs drives 3 SLBs Means 24 channels/FPGA, or 8 fibers feeding 1 FPGA

3. CMS/CERN. Nov, 2001HCAL TriDAS3 HCAL FE/DAQ Overview Shield Wall CPUCPU DAQ RUI HPD FE MODULE DAQ DATA SLINK64 [1 Gbit/s]  18 HTRs per Readout Crate FRONT-END RBX Readout Box (On detector) READ-OUT Crate (in UXA) Trigger Primitives: 8 towers/link Fibers at 1.6 Gb/s 3 QIE-channels per fiber QIE CCA GOL DCCDCC TTC GOL CCA HTRHTR HTRHTR HTRHTR CAL REGIONAL TRIGGER 32 bits @ 40 MHz CCA

4. CMS/CERN. Nov, 2001HCAL TriDAS4 HTR Schematic P1 LVDS Tx P3 SLB -PMC Trigger output 48 Trigger Towers Full 9U Board 8 FE fibers 24 QIE-ch’s to DCC 8 FE fibers 24 QIE-ch’s to DCC O-to-E FPGA Xilinx “Vertex 1000E” deS LVDS Tx O-to-E FPGA Xilinx “Vertex 1000E” deS P2

5. CMS/CERN. Nov, 2001HCAL TriDAS5 HTR Test Board 8 deSerializersDual LC (Stratos) Xilinx XCV1000E 6 SLB daughterboards (next version, these migrate to backplane card)

6. CMS/CERN. Nov, 2001HCAL TriDAS6 Tracker Scheme Lasers and single-mode fiber as pigtails 1 st connector serves to merge pigtails into 12-channel fiber ribbons 2 nd connector merges 8 12-channel ribbons into trunk cable for transport thru shield wall Magic Number: 12 How to make this fit? –Additional patch panel Makes 2x12  3x8? HTR use 2x4 per FPGA Need to verify that 4 channel Rx exists 8-channel Rx exists!

7. CMS/CERN. Nov, 2001HCAL TriDAS7 Issues Will GOL drive Tracker transmitter? –P. Moreira is investigating this now. Guess that it will, but so far… Time scale for parts? –Rx/Tx Link: Needed Q1 ’02 for prototyping (“eval board”) and testbeam (using GOL) –Trunk cable, connectors, etc, needed ~2004, not a problem Receivers –Noone has made a 1.6 Gbps TI receiver work with this detector/amplifier But it should work…just noone has done it. “Patch Panel” –What is involved? We want to use the magic number 12 on the Tx side, and 8 on the Rx side, and keep flexibility for mapping. –Single-mode fibers are ~10  m – alignment issues The tracker group believes this is fine. –Cost? HCAL needs digital, tracker uses analog

8. CMS/CERN. Nov, 2001HCAL TriDAS8 Cost Savings M&S –Current scheme: $176/link –Tracker scheme: $125/link Does not include additional patch panels (cost goes up) Does not include digital v. analog parts (could go either way) –Difference: $51/links 3048 links in HCAL Total cost savings around $150k – modest…. –Patch Panel? Do we really not need it now? It would cost plenty for the “Tracker Solution” Additional engineering –New layout with new O-to-E Maybe not so much if present HTR board works. 1 month FTE? ($12k) –Checkout If it works…this is minimal (0-1 month FTE) (0-$12k) –Test cards If we have to engineer this, it will take 6 months ($60k) –Total engineering costs: $12k - $84k depending….