Nicola Bacchetta September 24, 02 DOE review1 Baseline Readiness Review September 24, 2002 Nicola Bacchetta INFN-Padova and Fermilab Run IIB Silicon Project Co-leader For the CDF collaboration Run IIb Silicon Upgrade: Technical Presentation

Nicola Bacchetta September 24, 02 DOE review2 Run IIb Silicon - Outline uOverview of Goals and Constraints uLayout uStave Concept uComponent Details uL0 design uConclusions

Nicola Bacchetta September 24, 02 DOE review3 uIn the fall 2000 a working group was formed to calculate the longevity of the IIa silicon detector èIIa cannot survive above ~4 fb -1 uRadiation damage consequences with the new detector: èSensors should operate at high voltage(~350V). èSensors should be directly cooled (~-5C) èIC circuits in the detectors need higher level of radiation tolerance. uTo cope with higher doses during runIIb we need: èNew readout chip (1/4um tech.) èSingle sided sensors operating at high voltage èNew H/L voltage distribution system èNeed to directly cool the silicon uPresent technology allows all of the above to be achieved. Radiation Tolerance Implications IIb conditions:  L = 2-4  cm -2 sec -1 at 396ns or L = 5  cm -2 sec -1 at 132ns  ∫L = 15fb-1

Nicola Bacchetta September 24, 02 DOE review4 Silicon Upgrade for Run IIb uDesign Goals: èRobust, simple, flexible and reliable design èMinimize the cost èMatch or exceed performance of Run IIa silicon detector èMinimize changes to infrastructure: DAQ or cooling systems èIntegrate CDF experience from SVX, SVX’ and SVXII èPursue common solutions with D0: –Svx4 chip –Technology of silicon –Direct cooling –Hybrid technology –L0 technology

Nicola Bacchetta September 24, 02 DOE review5 RunIIb Layout uFinal layout choices are the results of many internal reviews with inputs also from Laboratory committees. uMain Layout Choices: è6-fold symmetry è1 stave design for all 5 outer layers èFill all space available up to ISL èMaximum flexibility in the choice of Axial/Stereo layers èInnermost layer (L0) similar to the present L00

Nicola Bacchetta September 24, 02 DOE review6 Run IIb Layout Details 94% of sensors and hybrids are 4-chip

Nicola Bacchetta September 24, 02 DOE review7 RunIIb Layout uEmphasis on simplicity and flexibility u Easy to be mass produced uMinimum number of parts: è1 hybrid (4 chips) è2 sensors (axial and stereo) Single stave design: èMinimize R&D èMinimize tooling èMinimize production time Carbon fiber bulk-heads with inserts for precision alignment of staves

Nicola Bacchetta September 24, 02 DOE review8 Stave: conceptual view Mounting holes Chips Hybrid Pitch Adapter Cooling tubes Wing Cable Mini PC Mounts Sensors 2 sensors + hybrid = 1 module 3 modules per side 1 MPC per stave 1 readout unit per stave Stave is 66 cm long

Nicola Bacchetta September 24, 02 DOE review9 Stave:end view Hybrid electronics Foam core Peek Cooling channels 2.9 x 5.6 mm Silicon Sensors 4mm separation Material/stave:  1.8% RL  124 grams Fraction of Total RL:  Sensors 39%  Hybrids 13%  Bus Cable 17%  CF/Coolant 29%

Nicola Bacchetta September 24, 02 DOE review10 Stave:cooling issues uTemperature specs for silicon: èKeep silicon cool to limit the amount of noise increase due to leakage current and limit the reverse annealing effect èStudies of these effects set temperature limits: –Layers 4-5: T<15 o C –Layers 2 and 3: T<10 o C –Layers 0 and 1: T<-5 o C èRequires active cooling of silicon uStave design incorporates cooling tubes (Peek) which meet specs uTotal heat load very similar to Run IIa ~3KW uPlan to use existing cooling system with increased glycol concentration (43%) for operation at -15 o C

Nicola Bacchetta September 24, 02 DOE review11 Barrel assembly Outer Bulkhead 2 mm thick CF (z = 66 cm) Inner Bulkhead 1 mm thick CF (z = 0 cm)

Nicola Bacchetta September 24, 02 DOE review12 Barrel in Spacetube z = 0 z = 66 cm z = 100cm Spacetube (CF +core) Similar to Run IIa Two half cylinders – glued together Supports weight of barrels Attaches to mount points on ISL end flanges

Nicola Bacchetta September 24, 02 DOE review13 Layer 0 Design uInner Layer (L0) follows Run IIa L00 design: èSmallest possible pitch – 25/50 micron pitch èFine pitch cables connect sensors to hybrids èHybrids are located out of tracking volume (~z=70cm) èPositioned at small radius (2.1 cm) èHybrids ~similar to outer layer, but 2 chips èWill be supported by outer barrel (not beampipe) uLow mass construction is of utmost importance for 1 st measurement uSensors are identical to L00 sensors uCables: èAll cables designed and the longest has been fabricated by KeyCom (Japan) èSome technical issues with the L0 cable sorted out BUT yield must be improved èWe are pursuing other possible vendors with also the option of splicing the cable.

Nicola Bacchetta September 24, 02 DOE review14 L0 Layout Sensors Fine pitch cables  Max. length 59cm  100um pitch  50um pitch at ends Hybrids Beampipe and CF support Cooling tubes L0 Module - 2 sensors + Fine pitch cables + one hybrid = one readout unit

Nicola Bacchetta September 24, 02 DOE review15 L0 hybrids and cables Cable flare out in radius (to ~4cm) after passing through bulkhead Cables from successive modules pass underneath hybrids from lower z modules Cooling tubes integrated into hybrid support structure

Nicola Bacchetta September 24, 02 DOE review16 Run IIb Status –outer layers uOur r&d effort pivots on the stave tests uAll stave prototype parts are in hand: èPrototype sensors èPrototype Hybrids èPrototype module fixtures are ready and tested èPrototype Bus cables èPCB version of the mini Port Card (BeO version expected at the end of September) èPrototype stave cores èTest Stands (= final DAQ system) are ready and used for testing uMain point is to verify the noise coupling between the Silicon and the Bus Cable. uExpecting results in late October  2 Prototype modules built (9/13)

Nicola Bacchetta September 24, 02 DOE review17 Silicon Sensors All detectors are single sided and based on the high voltage operation layout (CMS,ATLAS,L00) èEasy to build, test and handle èMinimal R&D necessary èPrototype (identical to final sensors) already in hand èHigh yield and high quality (0% bad channels grade “A” and 0.07% grade “B”) èFull charcterization in progress (radiation damage studies in early October)

Nicola Bacchetta September 24, 02 DOE review18 SVX4 chip uIt is a 0.25um translation of the SVX3d chip uDesign started in fall 2000 as a collaboration between LBL, FNAL and INFN-Padova. B.Krieger (LBL) lead engineer. u1st full prototype submission in April ‘02 uChip back in June ‘02 èTested both at LBL and FNAL èNo major problems found (so far) èSome adjustment required to meet production quality

Nicola Bacchetta September 24, 02 DOE review19 Hybrids uHybrids are fabricated on a Beryllium Oxide substrate for improved thermal performance and long radiation length. uHybrid layout uses advanced fine pitch technology for reduced area. uIntegrate SVX-II (a) experience into design, materials choices, and components to enhance reliability and simplify fabrication, assembly, and test. uHybrid appears to work with no apparent problem seen yet. uSVX4 chip performance on hybrid same as single chip on test board.

Nicola Bacchetta September 24, 02 DOE review20 Mini Port Card uUses the same BeO substrate as the hybrid uConnects to the top and bottom bus cable (directly and via a foldable “wing”cable) uControls all data, commands and power going in/out of the stave uAn FR4 version has been produced to allow start of electrical stave tests. uBeO prototype expected by end of September u5 transceiver chips are mounted for data control uTransceiver: èA new (0.25um) transceiver chip has been designed and submitted to MOSIS èNew transceiver simplifies connectivity and eliminates the need for an extra power line èNew transceiver fits in the silicon space left over by the svx4 chip èMPC is also compatible with the old transceiver which we have already plenty left over from IIa

Nicola Bacchetta September 24, 02 DOE review21 Module uFirst two modules fully assembled uMechanical procedures are satisfactory uPreliminary results confirm our expectations.

Nicola Bacchetta September 24, 02 DOE review22 Summary of Run IIb design uNew naturally Radiation hard chip required for Run IIb luminosity. èPrototype is in hand and functioning well! uDAQ simplified wrt Run IIa èNo optical components èNew Power Supplies: off-the-shelf, not custom èNumber of readout chains (252) much lower than available in existing infrastructure (408): more spare parts will be available ! uUniform stave design for ~94% of the detector èOnly one type of fixturing to develop for outer layers èL0 ~ L00 type construction uSmall number of different style parts èOnly 2 types of hybrids – 4 chip on outer layers, 2 chip on Layer 0 èL1-5 have 2 sensor types (axial and small angle) èL0 sensors = L00 sensors.

Nicola Bacchetta September 24, 02 DOE review23 Conclusions uGreat effort put into design simplification, ease of construction and low risk technology uDesign relies heavily on experience with previous silicon detectors at CDF (SVX, SVX’, SVXIIa, L00 and ISL) uWe expect the total mass in the tracking volume to be below the present value in spite of the increased number of sensors and need for direct cooling uDAQ simplified, active components are more accessible uAll prototype parts are in hand and testing is under way uPreliminary test results agree with expectations!