ELEC 7950 – VLSI Design and Test Seminar Multi-cycle scan based testing - Perik Patva ELEC 7950 – VLSI Design and Test Seminar 04-06-2016

Background Due to advancements in technology, the modern ICs have been highly influenced by the process variations and manufacturing defects. There are many techniques and methods currently used in the industry to detect these defects. However, there are many hard to detect open defects which are important contributors of test escapes.

Testing of sequential circuits Most of the modern ICs are tested using a scan design. It helps in controllability and observability of flip-flops and hard to access internal nodes of a circuit. All the flip-flops are connected serially to form a shift register which is known as scan chain. A multiplexer selects the data during the functional mode while it selects the scan input during the scan mode.

Full scan design for sequential circuits

Transistor stuck-open (TSOP) faults Stuck open fault can be considered as some open (break) at the terminals of a transistor. It can result from a break in connection within cells of the standard library. Consider a PMOS at the input A to be stuck-open.

Transistor stuck-open (TSOP) faults It requires two vector test: 1.) v1 - Initialize the output 2.) v2 - Activate and propagate the fault at primary output. Two pattern test for this fault is v1 = 1,1 and v2 = 0,1 A B Out 1 1 0/0 0 1 1/0

LOC and LOS testing In both methods, v1 is scanned in with SE asserted. In LOC, v2 is generated through combinational logic with SE signal set to low. In LOS, v2 is generated by shifting the scan chain by one bit with SE asserted.

Example illustrating multi-cycle testing Consider a NAND gate connected to a flip-flop as shown in figure below. The TSOF fault at input A is detected only after third consecutive clock cycle. The sequence 0 1 1 at the PI will detect the fault. B X 0 1 PO PI 0 1 1 A 1 1 0/1 0 1 1 FF 0 1 1 X 0 1

Multi-cycle LOC testing The initialization vector v1 is scanned in just as standard LOC testing. It is followed by m functional clock cycles with SE signal set to low.

Multi-cycle LOS testing The initialization vector v1 is scanned in just as standard LOS testing. The second vector is applied by shifting the scan chain by one bit followed by m-1 functional clock cycles with SE set to low.

Enhanced scan design Additional flip-flop is added with every scan flip-flop. Arbitrary two-pattern tests <v1, v2> can be applied.

Test Coverage of TSOF faults Experimental Results Test Coverage of TSOF faults Test Coverage s1423 s9234 s15850 s35932 s38584 Average Standard LOC 82.50% 84.41% 76.5% 97.27% 87.76% 85.69% Multi-cycle LOC 91.37% 89.84% 84.34% 99.77% 96.68% 92.40% % increase 8.87% 5.43% 7.84% 2.50% 8.92% 7.76% Standard LOS 86.38% 96.76% 98.24% 99.92% 99.32% 96.12% Multicycle LOS 91.87% 97.12% 99.93% 99.35% 97.30% 5.49% 0.36% 0% 0.01% 0.03% 1.18%

Number of test patterns Experimental Results Number of test patterns No. of patterns s1423 s9234 s15850 s35932 s38584 Average Standard LOC 111 480 367 130 459 - Multi-cycle LOC 79 409 286 68 404 % reduction 28.83% 14.79% 22.07% 47.69% 11.98% 25.07% Standard LOS 116 429 470 139 454 Multicycle LOS 71 366 401 59 350 38.79% 14.69% 14.68% 57.55% 22.91% 29.72%

Conclusion TSOFs at some fault sites may require multiple fault activation cycles. This method can give higher test coverage of stuck-open faults and requires less number of test patterns thus reducing the test time.

Future work In the method described earlier, after applying first vector, the additional vectors are applied using capture cycles with SE asserted. But, there could be some instances where the multi-cycle test can be done with m-1 shift cycles followed by capturing the response in the last cycle by setting SE low. This may result in higher test coverage.

References Z. Zhang, S M. Reddy, I. Pomeranz, X. Lin, and J. Rajski, “Scan tests with multiple fault activation cycles for delay faults,” in Proc. IEEE VLSI Test Symp., Apr.–May 2006, pp. 343–348. M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000. Chao Han, "Testing and Diagnosis of CMOS Open Defects in the Presence of Common Hazards,“ Auburn University, July 2015. Chao Han, and Adit D. Singh. "Improving CMOS open defect coverage using hazard activated tests." VLSI Test Symposium (VTS), 2014 IEEE 32nd. IEEE, 2014. Gefu Xu, and Adit D. Singh. "Low cost launch-on-shift delay test with slow scan enable." Test Symposium, 2006. ETS'06. Eleventh IEEE European. IEEE, 2006. Wei Wang, “Multiple Cycles Scan Tests for Stuck Open Faults”, Auburn University, April 2015. Xijiang Lin, Sudhakar M. Reddy, and Janusz Rajski. "Using Boolean Tests to Improve Detection of Transistor Stuck-open Faults in CMOS Digital Logic Circuits." VLSI Design (VLSID), 2015 28th International Conference on. IEEE, 2015. Ashok Kumar Suhag and Vivek Shrivastava. "Performance evaluation of delay testable enhanced scan flip-flop." International Journal of System Assurance Engineering and Management 3.3 (2012): 169-174. Victor Champac, et al. "Testing of stuck-open faults in nanometer technologies.“ Design & Test of Computers, IEEE 29.4 (2012): 80-91.