1. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 1 This courseware product contains scholarly and technical information and is protected by copyright laws and international treaties. No part of this publication may be reproduced by any means, be it transmitted, transcribed, photocopied, stored in a retrieval system, or translated into any language in any form, without the prior written permission of Acehub Vista Sdn. Bhd. or their respective copyright owners. The use of the courseware product and all other products developed and/or distributed by Acehub Vista Sdn. Bhd. are subject to the applicable License Agreement. For further information, see the Courseware Product License Agreement. http://dreamcatcher.asia/cw ME2500 DESIGN FOR TESTABILITY

2. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 2 3. DfT Structures for Delay Testing Prof. A Richardson: A.Richardson@Lancaster.ac.uk

3. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 3 Outline Principles of delay testing Vector Clocking Strategies –Launch on Shift –Launch on Capture DfT Structures for Delay Testing –Muxed-D Scan –Enhanced Scan Delay Fault Models Summary and References

4. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 4 3.1 Principles of Delay Testing

5. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 5 3.1 Principles of Delay Testing Also referred to as AC testing or Broadside Test. –Note: Broadside Test is traditionally defined as a scan-based test methodology involving two vectors Basic Principles are as follows: –First vector used as a stimuli, the second vector being the response of the combinational block to the first vector. –Broadside test will “propagate” a slow-to-rise or slow-to-fall transition to an output. These effects manifest themselves as transition faults. –Transition faults can be due to resistive opens or shorts, via voids and gate oxide failures. Nanometer technologies are more sensitive to transition faults due to increased systematic and random process variations.

6. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 6 Approaches to Delay Test –Random Advantages: No ATPG needed; hence, BIST is possible. Disadvantages: poor coverage of longest circuit paths, causes high circuit activity (power, temperature) –Functional Applied at rated clock speed, can utilise on chip memory / cache to hold functional patters Expensive requiring normally fully features testers –Structural Uses delay fault model & knowledge of the physical circuit structure. Must include DfT. Chip functions differently to normal operation. This lecture focuses on DfT-enabled structural delay test, the industry standard

7. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 7 Structural Delay Test: Basic Principles As with Broadside Test, two vectors are used. –First vector V1 initialises the logic; the second vector V2 launches a transition. –Response from V2 is captured back in the scan chain by a fast clock that can then be scanned out and compared with the expected response Problems with Structural Delay Test –Not all V1; V2 combinations can be applied due to architectural limitations of scan –In addition to Broadside test, that uses a Launch on Capture approach, Launch on Shift strategies are also now commonly used.

8. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 8 3.2 Vector Clocking Strategies

9. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 9 Vector Clocking Strategies Launch on Shift (LOS): –V2 generated by a 1-bit shift; hence V2 is limited to a 1-bit change in the initialisation vector V1. –Requires the scan enable signal to transition at speed between the shift mode (needed to launch vector) and functional mode (needed to capture response) Launch on Capture (LOC): –V2 is the response of the combinational block to vector V1 –Still restrictive regarding the values of V2 limiting coverage

10. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 10 Vector Clocking Strategies (cont.) Advantages of Launch on Shift –Combinational ATPG can be used with minor modifications to enforce the test patterns needed –Minimal vector generation time as the transition vector is derived from the initialisation vector Disadvantages of Launch on Shift –Must flip the scan cells from scan mode to normal mode at system clock speed increasing area and power consumption Advantages of Launch on Capture / Broadside Test –No timing constraints on the speed of the scan enable circuits –Test vector derived from Primary Outputs eliminating false paths Disadvantages of Launch on Capture / Broadside Test –Vector generation involves backtracking 1 clock cycle to generate the initialisation vector — more complex

11. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 11 3.3 DfT Structures for Delay Testing

12. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 12 3.3 DfT Structures for Delay Testing There are two main architectures to support Delay Test: Muxed-D scan: –This is a low area overhead architecture that requires a standard scan-chain architecture where the latch inputs are fed by a 2:1 multiplexor with one channel being the PPO’s and the other the scan data in (see slide 13). The latch outputs feed the PPI’s. –The disadvantage is PPI’s change on each clock increasing power consumption; advantages are that the system clock drives both normal and test modes Enhanced scan: –Hold latches placed in series with the scan latches to isolate the scan chain from the circuit under test (slide 20). The advantage is that PPI’s do not change during loading of the scan chain thus reducing power.

13. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 13 SE CK X1 SDI Combinational Logic DI Q SE SI DI Q SE SI DI Q SE SI X2 Xn Y1 Y2 Yn PPO PPI Advantages: System clock is used in normal and test modes Low area overhead Disadvantages: PPI’s change with each shift Delay Test Based on Standard Muxed-D Scan

14. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 14 Muxed-D Architecture (1) In LOC mode –To launch a transition, normal functional clock is used with SE enabled. –First Vector initialises the logic, SE is toggled, CLK is pulsed to apply the circuit response to the PPI’s (transition vector) –CLK pulsed again AT-SPEED to capture response. Problem: transition vectors limited to response from V1, and PPI’s change with each shift

15. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 15 LOC Timing Diagram Here SE remains high long enough to allow V1 to be scanned in. SE goes low before V2 launch edge to allow the output from the V1 vector to stabilise at the D-inputs (this is the new vector V2). V2 is launched by the system clock and the result captured; then SE goes high, and the result is scanned out. CLK SE Scan-in cycle Launch Cycle Capture cycle scan-out cycle V1 V2 launch edge Capture edge

16. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 16 Muxed-D Architecture (2) In LOS Mode –Flip-Flop inputs only connected to PPO’s and neighbour scan cells. –Transition vector can be derived by applying a functional clock pulse to the scan chain rather than using the PPO outputs. –In this case the SE signal must be pulsed AFTER application of V2 A-SPEED to ensure the PPO response is captured at circuit speed. –LOS is however ATPG friendly Key Limitation SE must be flipped at system speed (area, power constraint) — LSSD can help (separate SE for inputs / output capture). Also false long paths may be exercised.

17. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 17 LOS Timing Diagram Note: Scan-in runs at a slower speed; V2 launch and capture is however at speed. In MUXED-D, capture is in the same Flip-Flops, CLK SE Scan-in cycle Launch Cycle (last scan-in cycle Capture cycle scan-out cycle V1 V2 launch edge Capture edge

18. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 18 Enhanced Scan Supports LOS strategies by interleaving “redundant” flip-flops with the normal scan flip-flops –Allows V1 and V2 to be simultaneously scanned in –Very expensive in terms of silicon area Combinational Logic FF SFF FF FFF SFF Scan In PI’s PO’s Conventional Enhanced Scan — FF pairs in dashed boxes

19. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 19 Alternate Enhanced Scan Instead of redundant flip-flops, use HOLD cells with separate enable signals attached to each Scan Flip-Flop. Supports the loading of V1 in the HOLD cell; several shifts on the scan chain to load V2 then application of V2 through the ENABLE signal on the HOLD CELL Still high area overhead; also the HOLD cell must be FAST to ensure that the delay associated with the launch of V2 is much smaller than the AT-SPEED clock period.

20. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 20 UPDATE SE CK X1 SDI DQ C Combinational Logic DQ C DQ C DI Q SE SI DI Q SE SI DI Q SE SI X2 Xn Y1 Y2 Yn Operation: Scan initialisation vector into flip-flops Apply initialisation vector via “update” Scan test vector into flip flops Launch transition using “update” Alternate Enhanced Scan (cont.)

21. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 21 LOS and LOC Procedures LOS –Set circuit under test to scan mode; scan initialisation vector in –Apply 1 system clock to shift scan chain 1 bit –Flip SE and pulse system clock to capture PPO values –Set circuit under test to scan mode and shift out results LOC –Set circuit under test to scan mode; scan initialisation vector in –Set SE to normal mode; insert dummy clock cycles to give SE time to flip –System clock pulsed twice; First, test vector is derived from the initialisation vector; Second, results captured –Set circuit under test to scan mode and shift out results

22. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 22 3.4 Delay Fault Models

23. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 23 Delay Fault Models Transition Faults –Each input or output assumed to have a slow to rise or slow to fall delay fault — delay assumed large — i.e., will exceed the slack of the shortest path through that line –Disadvantage: resolution is limited by the difference in delay between the longest and shortest paths through the fault site In-line delay fault –Only the STR or STF mode of the TF –Produces shorter test sets — targets resistive vias Gate delay model –Local delay fault due to spot defect — need to test through a transition on the longest path through the fault site

24. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 24 Delay Fault Models (cont.) Path Delay Fault –Abstracts the fault to a distributed delay — covers the other fault models but implies all paths must be excercised (can be very large and include false paths) Defect Delay Fault Models –More accurately model real defects but complex to use, cover local and global disturbances, crosstalk, resistive and capacitive vias, etc.

25. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 25 3.5 Summary and References

26. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 26 Summary The overhead associated with Enhanced Scan can be reduced through Partial Enhanced Scan (ref. Han et al 2011) The limitations of using LOS with conventional D-Muxed scan chains can be addressed through design (ref. Kumar et al 2010) We have identified a number of fault models that can be used to generate delay test vectors Key will be further uptake of defect models to better reflect defect mechanisms in sub 60 nm technologies

27. © Copyright 2012 Prof. Andrew Richardson & Dream Catcher Consulting Sdn. Bhd. 27 References M. L. Bushnell and V. D. Agrawal; "Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits", Springer, 2000. Wang, Stroud & Touba “System on Chip Test Architectures” Morgan Kaufmann, ISBN: 978-0-12-373973-5, 2008. Chao Han; Singh, A.D.; Singh, V.; "Efficient partial enhanced scan for high coverage delay testing," System Theory (SSST), 2011 IEEE 43rd Southeastern Symposium on, vol., no., pp.243-248, 14-16 March 2011. Savir, J.; Patil, S.; "On broad-side delay test," VLSI Test Symposium, 1994. Proceedings., 12th IEEE, vol., no., pp.284-290, 25-28 Apr 1994 Kumar, R.; Khatri, S.P.; "An efficient pulse flip-flop based launch-on-shift scan cell," Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, vol., no., pp.4105-4108, May 30 June 2nd 2010 Kumar, R.; Khatri, S.P.; "An efficient pulse flip-flop based launch-on-shift scan cell," Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, vol., no., pp.4105-4108, May 30 2010-June 2 2010