1. Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing Adit D. Singh Gefu Xu Auburn University

2. IC Testing is a Difficult Problem  Need 2 3 = 8 input patterns to exhaustively test a 3-input NAND  2 N tests needed for N-input circuit  Many ICs have > 100 inputs  Only a very few input combinations can be applied in practice 2 100 = 1.27 x 10 30 Applying 10 30 tests at 10 9 per second (1 GHZ) will require10 21 secs = 400 billion centuries! Applying 10 30 tests at 10 9 per second (1 GHZ) will require 10 21 secs = 400 billion centuries! 3-input NAND

3. How well must we test? Approximate order-of-magnitude estimates  Number of parts per typical system: 100  Acceptable system defect rate: 1% (1 per 100)  Therefore, required part reliability  1 defect in 10,000  100 Defects Per Million (100 DPM) Requirement ~100 DPM for commercial ICs Requirement ~100 DPM for commercial ICs ~500 DPM for ASICs ~500 DPM for ASICs

4. How well must we test? Assume 2 million ICs manufactured with 50% yield  1 million GOOD >> shipped  1 million BAD >> test escapes cause defective parts to be shipped parts to be shipped  For 100 BAD parts in 1M shipped (DPM=100) Test must detect 999,900 Test must detect 999,900 out of the 1,000,000 BAD parts out of the 1,000,000 BAD parts For 100 DPM: Needed Test Coverage = 99.99%

5. Defects Detected by Different Tests  Number of Defects (DPM) found by individual additional tests in high end die after screening by high quality stuck-at tests DPMDPM 1000-10000 500-5000 100-500 Burn-in Delay N-detect Bridging 100-500 Target DPM 500 - 50

6. Scan Based Delay Tests Also  Good functional timing tests are difficult to develop  At-speed testers are expensive Scan-based delay testing is essential for SOCs  Because of insufficient access to cores for application of at- speed functional tests

7. Timing or Delay Tests Timing or Delay Tests  Two-pattern test vectors cause a change at the outputs  Switching delay is the time from the application (launch) of V 2 until change at the output  Worst case switching delay < clock period V 1 V 2

8. Scan Based Delay Testing  Restricts the two pattern tests that can be applied  Launch - on - shift (LOS) V2 : 1-bit scan shift of V1 V2 : 1-bit scan shift of V1  Launch - on - capture (LOC) V2: functional response to V1 V2: functional response to V1  Restriction makes it harder to apply “worst case” delay tests Comb. Logic Scan FFs Launch Capture V1 R[V1]

9. MUX FlipFlop Data In ScanEnable Scan In Data Out Clock LOGIC Launch-on-Shift Clock Edge 1: Launch V2 (scan = 1) Then switch scan = 0 Clock Edge 2: Captures response to change in Flip Flop V1 V2

10. MUX FlipFlop Data In ScanEnable Scan In Data Out Clock LOGIC Launch Clock Edge 1: Launch V2 (scan = 1) Then switch scan = 0 Clock Edge 2: Captures response to change in Flip Flop V1V2 V2

11. MUX FlipFlop Data In ScanEnable Scan In Data Out Clock LOGIC Capture Clock Edge 1: Launch V2 (scan = 1) Then switch scan = 0 Clock Edge 2: Captures response to change in Flip Flop V2

12. MUX FlipFlop ScanEnable Scan In Clock LOGIC Launch-on-Capture Clock Edge 1: Apply V1 (scan = 1) Then switch scan = 0 Clock Edge 2: Capture response to V1 to launch V2 Clock Edge 3: Capture response to V2 V1 V2 = Response[V1]

13.  Two vector tests that test for rising and falling delays at every circuit node  Guarantee detection of “gross” delay faults that exceed a clock period  May not detect smaller delay faults that are absorbed within timing slacks on short paths Transition Delay Fault (TDF) Tests

14.  Despite the structural restrictions, scan based delay test can achieve LOC: 75 -90% TDF coverage LOC: 75 -90% TDF coverage LOS: 80 -95% TDF coverage LOS: 80 -95% TDF coverage  LOS tests also generally require fewer patterns TDF Coverage of Scan Based Tests

15. Summary of Delay Tests performed - LSI Logic IEEE D&T TDF and at-speed functional effectiveness comparison

16. Variations in CMOS Delays  CMOS delays greatly depend on the off path signals and internal circuit state  Hard to find to ensure worst case conditions for signal propagation along a path.  Often this worst case test vector pair can be different for the same circuit depending on fabrication parameters 3X variation in rise time

17. Finding tests for worst case signal propagation conditions  “Robust” path delay tests are logic level tests that account for many but not all worst case conditions - Robust Path Delay tests often do not - Robust Path Delay tests often do not exist for many (even majority) of the paths exist for many (even majority) of the paths  Many desired delay timing tests may be impossible to apply in a scan environment because of structural restrictions Problems in Delay Test Application

18. Input Based Path Delay Variations PATHPATH Delay T_critical clock average delay Timing margins to allow for parameter variations, clock skew, etc can make “small” defects undetectable Timing Margin 10% T_cr

19. Input Based Path Delay Variations PATHPATH Delay T_critical clock average delay Defects that increase path delay by less than 10-20% of T_critical are virtually undetectable Timing Margin 10% T_cr

20. Simulation Results for Launch-on-shift Yan [ITC 04]

21.  For a 8 level critical path, average gate delay 12.5% of T_critical 12.5% of T_critical  25% extra path delay implies a 200% increase in the delay for some gate - significant! - e.g. Via resistance must grow 1,000-10,000X - e.g. Via resistance must grow 1,000-10,000X from 0.1ohm (typical) to cause such a delay from 0.1ohm (typical) to cause such a delay  Simulations [Yan ATS 04] estimate about 50% will cause timing related functional failure for some untested input - many will also cause early life reliability failure - many will also cause early life reliability failure Are these “small” defects worth detecting?

22. DDSI: Delay Detection in the Slack Interval  Abnormal delays are observed in the slack interval  A delay defect need only be active to be detected – no need to set up worst case conditions to exceed the nominal clock period – no need to set up worst case conditions to exceed the nominal clock period V1 V2 Observation Clock Operational Clock Slack

23. Timing Simulation based Tests  Switching delays for each output obtained through timing simulation  Must add margins for process variations  Test repeated for multiple fast clocks V1 V2  Cadence “True Time” delay tests claim TDF ~ 80% sufficient for 2X DPM improvement sufficient for ~ 2X DPM improvement Accurate timing simulation difficult & expensive! Accurate timing simulation difficult & expensive! Fast Observation Clocks

24.  Delay detection is the slack interval solves the problem of detecting defects on “short” paths - huge simulation cost - huge simulation cost - margins for parameter variations limit - margins for parameter variations limit effectiveness effectiveness  Problem of “out of normal mode testing” still to be solved A Second Major Problem with Scan Based Delay Tests

25.  Scan based launch and capture delay tests place the circuit out of the normal functional operating mode which can significantly impact circuit performance and change observed delays  IR drops in power rail due to excess switching activity can slow logic and give false fails  Unto 20% delay variation from 40 o C temperature change  10-20% “clock stretch”  Unexpected coupling noise Scan Tests “Out of Normal Mode”

26. Proposed Solution: Timing Learned from Silicon  Same idea as simulation based DDSI method  Except timing “learned” from golden die  More accurate and less expensive than simulation V1 V2 Also automatically accounts for test conditions:  IR drops, temp variations, clock stretch, coupling, etc Fast Observation Clocks

27. Proposed Solution: Timing Learned from Silicon For each 2-vector delay test pattern, the switching time is learned from a “golden” die

28. Need Output Hazard Free Tests How a hazard can cause incorrect timing to be learned

29. Output Hazard Free Transition Tests  Output hazard free tests are less restrictive than robust tests  Test responses are only observed on outputs known to be hazard free  Philips has shown hazard free tests with ~ 50% TDF coverage with test filtering using fast timing simulation  Expensive to filter large test sets

30. What Coverage is Achievable from Output Hazard Free Transition Tests?  Masking of potential due to paths of differing lengths  Such potentially hazard free outputs are good candidates for test filtering

31. LOS Circuit Hazard-Free TDF (Lower Bound) Mode 3Mode 2Mode 1Mode 0 Unrestricted TDF S20860.1072.8478.3779.33 88.94 S29860.7462.92 64.6076.5184.23 S34482.7083.4385.7686.6387.5094.04 S34981.6682.3884.6785.5386.3993.41 S38270.9473.5675.7978.0183.3890.71 S38651.1754.7957.5158.1668.2679.40 S40068.6270.8873.6276.3882.1389.50 S42060.0075.8377.9878.5778.8187.74 S44459.5762.3963.4070.7277.7086.60 S51057.8463.1467.0674.4181.3790.39 S52665.7867.1168.2570.5380.1387.45 S526n65.8767.2168.3570.6380.0487.64 S64187.5291.1392.2392.5493.8096.70 S71353.0958.4959.7574.9676.7290.81 S82036.8338.4140.3044.0957.9978.17 S83236.0637.4439.3042.8556.9777.04 S95371.0981.1183.1684.4287.5191.03 S119657.8267.0269.0671.2874.3785.54 S123857.3165.0666.6068.8671.6181.99 S142376.8882.6482.7884.5091.2295.99 S148845.4351.3153.5356.7963.3179.67 S149444.4850.5052.6455.7662.4579.08 S537865.4568.7570.9875.2789.5993.05 S923464.7170.0171.2676.6080.0488.28 S1320778.2480.6681.2084.3187.4994.04 S1585075.6678.4578.7981.1782.1590.66 Ave.62.9167.5969.4372.5778.3487.77

32. LOC Circuit Hazard-Free TDF (Lower Bound) Mode 3Mode 2Mode 1Mode0Unrestricted TDF S20836.7848.0850.2450.72 57.45 S29854.1955.0357.5559.9070.3081.21 S34472.9777.4782.2784.5986.1993.75 S34971.9276.3681.0983.3884.9693.12 S38252.4953.2754.4556.8168.8576.83 S38634.9736.9237.8239.9041.7152.72 S40050.8851.6352.8855.2568.3775.63 S42028.2153.8154.8855.48 64.76 S44442.1243.4744.0353.4958.1175.11 S51055.0061.1863.9270.1075.4989.41 S52637.2637.7440.0243.5453.2364.35 S526n37.2637.7440.0243.5453.3364.35 S64180.4685.4886.3486.5088.0791.60 S71346.9154.6356.7368.0970.4885.13 S82032.8733.8434.9436.9543.4851.83 S83232.2733.2334.3836.3642.9151.08 S95370.4678.7080.9082.0685.9491.55 S119652.5561.0464.6766.7269.7381.65 S123850.8560.1063.2965.7968.3079.08 S142356.0161.3561.7466.0276.8887.10 S148842.0748.5951.3455.9562.3387.40 S149441.6747.8650.7755.0961.5586.98 S537873.6476.6186.6582.3586.6589.61 S923437.3344.0345.4952.4159.0074.71 S1320753.3456.4257.4363.8270.0182.38 S1585051.9158.6059.1762.1264.2378.82 Ave.49.8655.1257.4260.6566.0177.22

33. S537865.4568.7570.9875.2789.5993.05 S923464.7170.0171.2676.6080.0488.28 S1320778.2480.6681.2084.3187.4994.04 S1585075.6678.4578.7981.1782.1590.66 Ave.62.9167.5969.4372.5778.3487.77 S537873.6476.6186.6582.3586.6589.61 S923437.3344.0345.4952.4159.0074.71 S1320753.3456.4257.4363.8270.0182.38 S1585051.9158.6059.1762.1264.2378.82 Ave.49.8655.1257.4260.6566.0177.22 Circui t Hazar d-Free TDF (Lowe r Bound ) Mode 3 Mode 2 Mode 1 Mode 0 Unres tricte d TDF Circui t Hazar d-Free TDF (Lowe r Bound ) Mode 3 Mode 2 Mode 1 Mode 0 Unres tricte d TDF LOSLOC

34. Identifying Golden Die x x  Timing responses from two matched neighboring die are compared  If delays are with the expected range based on observed parameter variations the die are taken to be golden die xxx xxx Note: Response reflects test conditions!

35. Summary  Learning timing from silicon can allow effective delay testing that automatically accounts for the “non function” test conditions of scan based delay tests  Obtaining such timing requires output hazard free TDF tests which can be obtained with coverage ~10% below unrestricted scan based TDF tests  Learning timing from silicon can be much cheaper and more accurate that timing simulation of short paths and can better account for parameter variations

36. Questions?