Front Side Circuit Edit: state of the art Circuit editing of first silicon using FIB (focused ion beam) technology has become increasingly more common in IC industry. Editing ICs is a standard methodology in order to reduce IC develop- ment costs. Typically the request is to fix a design issue (to be ahead of the mask change), modifying a device to get pre-production engineering samples to the customer. IC microsurgery has moved into nano- surgery dimension and is getting more challenging. There are several techniques and methodologies that make device characte- rization and circuit modification possible from the Front Side (FS) and from the Back Side (BS). We describe in the poster techniques and methodologies developed for successful IC debug. A “circle” of key points for successful FS edit: Alignment to buried nodes and/or blind nodes; Controlled mill process to face up the continuous metal layers thickness reduction and interlayer distance; Planar and safe removal of a wide variety of dielectrics and changes of porous organic materials (a.k.a low-k); Flat removal of top aluminum metallization (a.k.a Alucap); Even removal of copper grains; Controlling of the overspray during conductor deposition; Fill Vias with low resistivity; The itemized methodologies will surely be helpful to increase CE success. To cope with next technology shrinks, R&D of FIB CE methodologies will become a must. Edit request Feasibility study with MAGMA-3DSAA A real case FS Edit Technology CMOS 90nm Al Cu/low-k process with 7Cu-Metal layers. Edit request to isolate a M1 GND net and re-connect it to a M2 metal 300µm faraway. All is located under two power planes and several multi-shape dummies. Execution through 2 levels of power planes that have been removed and isolated with an optimized Insulator deposition. Inside the 5.84x3.85µm 2 edit area two holes HAR like (0.2x1.25µm 2 ), have been performed to isolate the M1 GND. A must was to place the HAR holes within an accuracy of 100nm to avoid contacting nearby metals. Conclusion: the successful of the here CE has been a combination of: Restricted edit area Refernce as fine alignment EFUG Maastricht The Netherlands - MOTTA Lorenzo, CAPITANIO Emanuele STMicroelectronics Validation Laboratory, Via Olivetti, Agrate – Italy; DI DONATO Donato Sector Technologies, 2 Avenue de Vignate Gieres – France Edit under Power Planes Digital Insulator deposition 130 nm 260 nm 4.97µm Target is deep and narrow  Digital HAR  Endpoint Accuracy Weak Secondary electron imaging Fib Assist (Post Processing) Next Challenge References 1. Nobile Matteo, Motta Lorenzo, Capitanio Emanuele, Di Donato D. “Circuit edit through dummies is easier with this new method” EFUG TR Lundquist,VV Makarov, “Etching Copper & Not the Dielectric”EFUG 2003; 3. Flore PERSIN, Emmanuel PETIT, Didier RENARD, “Repeatability for probing first metal layers from top surface-CMOS65nm technology” 11° EFUG 2007 A working device after a succesful edit Reference: 1 Reference: 3 Reference: 2 For further information Please contact: STMicroelectronics Sector Technologies Edit area under Alucap Digital removal methodology Copper metals into low-k dielectrics Cu/Low-k chemistry for planar removal DEVICE EDITING CHALLENGE 0.2x1.25µm 2 3,85µm 5,84µm  A good edit plan  Right copper chemistry Nevertheless there is the know-how and the daily fibbing.  Digital HAR recipe  Efficient chemistry  Fine CAD alignment 45 nm technology D-Damascene New materials low-k/high-k films MEMS High stacks 32 nm technology 45 nm technology D-Damascene New materials low-k/high-k films MEMS High stacks 32 nm technology