TLU plans 21/03/20161 D. Esperante, Velo upgrade meeting

Motivation  Have a compact trigger logic unit in one board instead of tens of VME modules and lemo cables dangling around.  Easy configuration of trigger logic remotely with added functionalities such as test readout elements (TimePix + DUT) without beam (ie auto trigger).  Make the logic a bit generic such it can be attached to LHC like read-out systems.  Implement a TDC that provides timing information. 21/03/20162D. Esperante, Velo upgrade meeting

General scheme (1) 21/03/2016 Embedded system based on Altera Stratix II FPGA development board Control PC Readout PC GBE TLU data Ethernet Control data External input trigger signals from NIM logic Output trigger signals to telescope + DUT External veto signals 3D. Esperante, Velo upgrade meeting

General scheme (2) 21/03/2016 NIOS II processor SRAM (TDC data) SDRAM (control software) GBE TDC data (to be defined) Ethernet Control data via webservices Coincidence signal sampling + TDC + trigger generator External input trigger signals Output trigger signals Veto/enable signals DMA 4D. Esperante, Velo upgrade meeting

Signaling example 21/03/2016 Spill signal Spill Shutter signal Beetle trigger signal 40 MHz clock RO time 5D. Esperante, Velo upgrade meeting

GPP: General Purpose Pulser 21/03/2016D. Esperante, Velo upgrade meeting6 Burst length Dead time General purpose pulser (GPP) Programmable features: - Startup dead time. - Pulse length. - Inter-pulse dead-time. - Max pulse count. - Output delay in clock cycles. - With or without repetition. - Programmable multiplexor input to select several sources of enable/veto. - Programmable multiplexor input to select several sources of force cero output. - Force pull-down. Start dead-time Pulse output Enable signal Synch trigger Coincidences

GPP 2  Using several GPPs with multiplexor at the enable/veto and “force-pull down” inputs we can implement the different output signals:  Spill signal:  Long burst length.  With repetition.  Timepix shutter signal:  Burst length modulated by external “force ‘0’ output”.  Dead time = timepix readout time.  Beetle trigger signal:  Burst length = ‘1’.  Dead time = ‘0’.  Max counter.  Veto/enable multiplexors:  The Spill signal enables the “Timepix shutter” and the “Beetle trigger” signals.  The “Beetle trigger” max counter forces the pull-down of the “Timepix shutter”. 21/03/2016D. Esperante, Velo upgrade meeting7

Internal scheme (1) 21/03/2016 Coincidence signal sampling + TDC + trigger generator General purpose pulser (GPP) Signal detection and synchronization Internal pulse generator TDC1 CLK40 CLK80 RST EN Shutter 25ns trigger External veto/enable RST Coincidence Force pull-down Max-cnt 8D. Esperante, Velo upgrade meeting CLK160 CLK20 CLK40

The TDC (‘s) 21/03/2016 TDC Features: - Implementation based on multiphase clock based on multiple of 40MHz (240 MHz). Resolution around 1ns. See “High-Precision TDC in an FPGA using 192-MHz Quadrature Clock”, Mark D. Fries, John J. Williams, Nuclear Science Symposium Conference Record, 2002 IEEE. 10/12/2002; 1: vol bits time counter. - Some extra bits with extra status info. To be defined. - The scheme also defines the signal synchronization circuitry. 9D. Esperante, Velo upgrade meeting

21/03/2016D. Esperante, Velo upgrade meeting10

Time stamping of output signals  It may be helpful to record the time when a transition in any of the output signals ocurred. Two options:  A TDC per output signal. Too heavy.  Have a clock counter and use it as time stamp. 21/03/2016D. Esperante, Velo upgrade meeting11 Time stamper CLK40 TDC CLK40 Scatter-gather DMA ShutterTrigger

Other technical issues  In this first design make something simple that works:  All clocks synchronous.  Will not use fancy improvements in the logic which would increase the data Tx rate.  Later improvements:  Think about an architecture that permits the TDC and the pulsers work in different clock domains so an external input clock could be used to generate the trigger signal while keeping the TDC untouched.  Zero-suppression… 21/03/201612D. Esperante, Velo upgrade meeting

Other technical issues  NIM voltage levels compatibility:  Use LVPECL or build a small adapter board.  In the future, maybe we could build a plug-in board with the discriminators and coincidence units.  Output data format:  To be defined.  Software development needed:  Firmware for the embedded system.  TLU reader: the Rx software at the readout PC.  TLU controller: webservices based control (html page). 21/03/201613D. Esperante, Velo upgrade meeting

Status  Embedded system with the NIOS II processor, SRAM, SDRAM, Ethernet link working. GBE not implemented yet.  Writing the VHDL for the pulser and performing the functional simulations.  Still quite a lot to do…  I’ll be away for some weeks… 21/03/201614D. Esperante, Velo upgrade meeting