1. AIDA (mini) Trigger/Timing Logic Unit (mini TLU)
Introduction
Status
Plans
Summary

2. Introduction Provide Simple Timing/Synchronisation Interface
Builds on EUDET TLU
New for AIDA – synchronous mode ( clock/trigger/busy ) for high trigger rate
Better performance than EUDET TLU
Trigger rate > 1MHz sustained , > 10MHz instantaneous

3. Hardware Implemented as FPGA Mezzanine Card (FMC).
Plugs into off-the-shelf FPGA carrier
Four trigger inputs
Software adjustable threshold
Threshold and CFD
Three Device Under Test interfaces
Can be fanned out to up to 30 DUT interfaces in synchronous mode with external fanout.
Open Hardware, Open Firmware:

4. Hardware Currently only as boards bolted to plate
Design for box in progress

5. Hardware
LVDS  TTL converters exist.
This example from NIKHEF

6. (Santiago de Compostela)
Development Team
David Cussans
( Bristol )
Hardware/Firmware
Alvaro Dosil
(Santiago de Compostela)
Firmware
Francesco Crescioli
( LPNHE )
Software

7. David Cussans, EUDAQ Workshop, DESY
Synchronous Mode
25/11/2015
David Cussans, EUDAQ Workshop, DESY

8. TLU in action Operation with non-AIDA telescope:
Interfacing TORCH ( LHCb upgrade proposal ) DAQ with LHCb TimePix3 telescope.
Accepts clock and synchronization signals from LHCb telescope
Provides “AIDA synchronous interface” to DUT
Recording trigger information ( scintillator triggers and Cherenkov counters ) for a TOF prototype (TORCH)

9. AIDA TLU with non-AIDA Beam-Telescope
LHCb Timepix3
Telescope
Telescope
Clock/Sync
Fanout
AIDA TLU

10. Clock/Syncronization Fanout
Up to 30 DUT
Compatible with miniTLU (in synchronous mode)

11. Status – Hardware Ten AIDA miniTLU boards exist
Production organized and paid by DESY
Minor hardware bug on connector
correctable by external plug-in cable converter

12. Status – Firmware Synchronous mode implemented
EUDET implemented but poorly tested
TDC functionality tested (and works)
Granularity 780ps
Separate timestamp for each trigger input
Coincidence logic – 4 input LUT allows any combination of inputs.
Each input can be delayed and/or stretched before input to trigger logic

13. Status – Software Producer for EUDAQ written
Basic Functionality Present
Sustained trigger rate of 1MHz measured
Many hardware control registers implemented in producer
 Producer needs
Development
Testing
Almost certainly debugging…

14. Plans 2/3 firmware/software team moved on, but
In the process of recruiting Engineer to develop firmware and hardware for AIDA-2020
50% on AIDA-2020 for four years
Open ended ( will be renewed if Bristol continues to be funded for HEP instrumentation )
Current slow down in development should end soon.

15. Hardware Plans New version of mini-TLU
Bug-fixed connectors ( use standard HDMI - breaks strict FMC mechanical spec.)
On-board low-jitter clock generator
Port firmware to Xilinx 7-series FPGA ( Artix)
Better performance TDC
Probably easier move to 8 input TLU
Smaller FPGA board
Move towards “full TLU”
6-8 inputs
6 DUT interaces

16. Summary Aim: Simple hardware unit to make common beam-tests easier.
Basic functionality achieved
Needs further testing
TLU specification document available at