Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration.

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Presentation transcript:

Altera Technical Solutions Seminar 2000

Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration Intellectual Property Design Iteration Design Optimization Internet Interface Roadmap Quartus Demo

Agenda Introduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration Intellectual Property Design Iteration Design Optimization Internet Interface Roadmap u APEX 20K Family u Quartus Software u Design Example

APEX ™ 20K Overview

Gates User I/O EP20K100 EP20K160 EP20K200 EP20K300 EP20K400 EP20K600 EP20K K 100K 750K 500K 1M1M APEX 20K Device Family

MAX 7000 u Product Terms u Wide Fan-in u Fast State Machines MAX 7000 u Product Terms u Wide Fan-in u Fast State Machines FLEX 6000 u Interleaved LABs u LE Structure u I/O Structure FLEX 6000 u Interleaved LABs u LE Structure u I/O Structure FLEX 10K u Interconnect u Embedded Memory u High Density u Phase-Locked Loop FLEX 10K u Interconnect u Embedded Memory u High Density u Phase-Locked Loop APEX 20K The Best of All Worlds

APEX 20K Features  125-MHz System Performance  64-Bit, 66-MHz PCI Compliance  4-Level Continuous FastTrack ® Interconnect New Level of Routing Hierarchy New Level of Routing Hierarchy  Enhanced Phase-Locked Loop (PLL)  Advanced I/O Standard Support Includes SSTL-3, GTL+, LVDS, and More Includes SSTL-3, GTL+, LVDS, and More  MultiVolt™ I/O Interface  Advanced FineLine BGA Packaging

APEX 20K Devices 4,160 6,400 8,320 11,520 16,640 24,320 42,240 Logic Elements 53K 82K 106K 147K 213K 311K 541K RAM Bits ,152 1,664 2,432 4,224 Macrocells 250K 100K 750K 500K Gates User I/O 1M1M EP20K100 EP20K160 EP20K200 EP20K300 EP20K400 EP20K600 EP20K1000

APEX 20K Technology  SRAM Process  0.25 µ, 0.22 µ, 0.18 µ  6-Layer Metal  0.15-µ Devices Planned for 2001 Density of 2-Million Gates Density of 2-Million Gates

Density AND Speed APEX 20K Performance Performance (MHz) 8-Bit, 512-Point FFT 128 x 64 Dual-Port FIFO 16 x 16, 4-Stage Pipelined Multiplier 16-Bit, 8-Tap FIR Filter 16-Bit, Up/Down Loadable Counter

APEX 20K Is 66-MHz PCI Compliant  Electrical and Timing Compliant  64 Bits  Outputs Have Programmable Clamps 3.3-V Compliant if Clamps Are Connected 3.3-V Compliant if Clamps Are Connected

EP20K200EP20K200EP20K400EP20K400 EP20K100EP20K V Core V CC 0.25/0.22  EP20K1000EEP20K1000E EP20K600EEP20K600E EP20K400EEP20K400E EP20K200EEP20K200E EP20K160EEP20K160E EP20K300EEP20K300E EP20K100EEP20K100E 1.8 V Core V CC 0.18  APEX 20K Supply Voltage

MultiCore ™ Architecture LUT P-Term Memory LUT P-Term Memory LUT P-Term Memory LUT P-Term Memory LUT P-Term Memory LUT P-Term Memory LUT P-Term Memory LUT P-Term Memory LUT P-Term P-Term Memory LUT P-Term Memory FLEX 6000 Model MAX 7000 Model FLEX 10KE Model

Quartus Development System Altera’s Fourth-Generation Development Tool

Streamlined Design Flow  Workgroup Computing  NativeLink™ Integration with EDA Tools  Scripting  Incremental Compilation  Easy Floorplanning Linked to Design  Intellectual Property

Additional Quartus Features  Verification Native HDL Simulator / Timing Analyzer Native HDL Simulator / Timing Analyzer SignalTap™: Hardware Verification at Speed SignalTap™: Hardware Verification at Speed  Internet-Based Support Device Support Updates Device Support Updates Patch Notification Patch Notification Quick Solutions Quick Solutions Enhancement Requests Enhancement Requests Software Problem Reporting/Tracking Software Problem Reporting/Tracking

Performance Comparison of Quartus software Over 40% Increase in Design Performance with Quartus Software Version

Design Performance Roadmap for the Year 2000

APEX 20K & Quartus Summary  Revolutionary Architecture for Integration  Quartus Speeds Complex Designs to Market  1-Gbit Ethernet Switch Illustrates Capabilities