CEC 220 Digital Circuit Design Decoders, Encoders, & ROM Wed, February 19 CEC 220 Digital Circuit Design Slide 1 of 18

Lecture Outline Wed, February 19 CEC 220 Digital Circuit Design Decoders and Encoders Read-Only Memories (ROMs) Slide 2 of 18

Decoders Wed, February 19 CEC 220 Digital Circuit Design Slide 3 of 18 A 3:8 Line Decoder  A minterm generator!! MSB LSB How can we implement this with AND & OR gates?

Decoders Wed, February 19 CEC 220 Digital Circuit Design Slide 4 of 18 A 4:10 Line Decoder – w/ active Low Outputs No Output Decoded How can we implement this with AND & OR gates?

Decoders An Example Wed, February 19 CEC 220 Digital Circuit Design Slide 5 of 18 Realize the following functions using a 4:10 Decoder

Encoders Wed, February 19 CEC 220 Digital Circuit Design Slide 6 of 18 An Encoder performs the inverse function of a Decoder  A priority encoder “prioritizes” the inputs while encoding Assume that y 7 is given the highest Priority y7y7 y6y6 y5y5 y4y4 y3y3 y2y2 y1y1 y0y0 abcdy7y7 y6y6 y5y5 y4y4 y3y3 y2y2 y1y1 y0y0 abcd 1XXXXXXX111 y7y7 y6y6 y5y5 y4y4 y3y3 y2y2 y1y1 y0y0 abcd 01XXXXXX110 1XXXXXXX111 y7y7 y6y6 y5y5 y4y4 y3y3 y2y2 y1y1 y0y0 abcd 001XXXXX101 01XXXXXX110 1XXXXXXX111 y7y7 y6y6 y5y5 y4y4 y3y3 y2y2 y1y1 y0y0 abcd X XX XXX XXXX XXXXX101 01XXXXXX110 1XXXXXXX111 y7y7 y6y6 y5y5 y4y4 y3y3 y2y2 y1y1 y0y0 abcd X XX XXX XXXX XXXXX XXXXXX1101 1XXXXXXX1111

Read-Only Memories (ROMs) Wed, February 19 CEC 220 Digital Circuit Design Slide 7 of 18 Read-Only Memories  n-address lines  2 n address locations each storing a “word”  m-output lines  m-bits are stored at each address location o Each word is m-bits long ROMPROMEPROMEEPROM NAND Flash NOR Flash

Read-Only Memories (ROMs) Wed, February 19 CEC 220 Digital Circuit Design Slide 8 of 18 An Example  3 address lines: 2 3 = 8 Words or storage locations  4-bits are stored in each “word”

Read-Only Memories (ROMs) Wed, February 19 CEC 220 Digital Circuit Design Slide 9 of 18 Basic ROM Structure

Read-Only Memories (ROMs) An Example Wed, February 19 CEC 220 Digital Circuit Design Slide 10 of 18 Develop a HEX (4-bits) to ASCII (7-bits) code converterASCII  How many input (address) lines do we have? o Answer: 4  How many memory locations will we have? o Answer: 2 4 = 16  What is the size of the word stored in each memory location? o Answer: The size of an ASCII code = 7-bits Memory Array 2 4 words X 7-bits … HEX Number ASCII

Read-Only Memories (ROMs) An Example Wed, February 19 CEC 220 Digital Circuit Design Slide 11 of 18 Develop a HEX to ASCII code converter A 5 =A 4 X

Examples Wed, February 19 CEC 220 Digital Circuit Design Slide 12 of 18 Implement a 4:1 MUX, using four tri-state buffers and a 2:4 decoder. 4:1 MUX I0I1I2I3I0I1I2I3 A B Z 2:4 Decoder

Examples Wed, February 19 CEC 220 Digital Circuit Design Slide 13 of 18 Which lines should be used as inputs to allow the :10 line decoder to be used as a 3:8 decoder?

Examples Wed, February 19 CEC 220 Digital Circuit Design Slide 14 of 18 What size ROM is required to implement the 4-to-10 line decoder?  How many inputs? o How many words?  How many outputs? o How many bits per word?

Examples Wed, February 19 CEC 220 Digital Circuit Design Slide 15 of 18 Use a ROM to implement an 8 bit priority encoder.  How many inputs? o How many words?  How many outputs? o How many bits per word?

Next Lecture Wed, February 19 CEC 220 Digital Circuit Design Programmable Logic Devices  PAL, PLA, CPLD, FPGA Slide 16 of 18