© Digital Integrated Circuits 2nd Devices Device Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. EE4271 VLSI Design

© Digital Integrated Circuits 2nd Devices Goal of this chapter  Present intuitive understanding of device operation  Introduction of basic device equations

© Digital Integrated Circuits 2nd Devices MOS Transistor Types and Symbols D S G G S D NMOS PMOS

© Digital Integrated Circuits 2nd Devices 4 Circuit Under Design

© Digital Integrated Circuits 2nd Devices Circuit on the Chip A transistor

© Digital Integrated Circuits 2nd Devices The MOS (Metal-Oxide-Semiconductor) Transistor Polysilicon Aluminum

© Digital Integrated Circuits 2nd Devices Simple View of A Transistor A Switch! |V|V GS | An MOS Transistor

© Digital Integrated Circuits 2nd Devices Silicon Basics  Transistors are built on a silicon substrate  Silicon forms crystal lattice with bonds to four neighbors

© Digital Integrated Circuits 2nd Devices Doped Silicon  Silicon is a semiconductor  Pure silicon has no free carriers and conducts poorly  Adding dopants increases the conductivity  extra electrons (doped Borons) – n-type  missing electrons (doped Arsenic/Phosphorus) more holes) – p-type n-type p-type

© Digital Integrated Circuits 2nd Devices NMOS Transistor Diffusion

© Digital Integrated Circuits 2nd Devices NMOS - II  Refer to gate, source, drain and bulk voltages as Vg,Vs,Vd,Vb, respectively.  Vab=Va-Vb  Device is symmetric. Drain and source are distinguished electrically, i.e., Vd>Vs.  P regions have acceptor (Boron) impurities, i.e., many holes.  N regions have donor (Arsenic/Phosphorus) impurities, i.e., many electrons.  N+ and P+ are heavily doped N and P regions, respectively.

© Digital Integrated Circuits 2nd Devices NMOS - III  Gate oxide are insulators, usually, silicon dioxide.  Gate voltage modulates current between drain and source, how?

© Digital Integrated Circuits 2nd Devices Enhancement NMOS

© Digital Integrated Circuits 2nd Devices Enhancement NMOS - II  Does not conduct when Vgs=0, except that there is leakage current.  When Vgs is sufficiently large, electrons are induced in the channel, i.e., the device conducts. This Vgs is called threshold voltage.

© Digital Integrated Circuits 2nd Devices Enhancement NMOS III Positively Charged Negatively Charged

© Digital Integrated Circuits 2nd Devices Enhancement NMOS - IV  When Vgs is large enough, the upper part of the channel changes to N-type due to enhancement of electrons in it. This is referred to as inversion, and the channel is called n-channel.  The voltage at which inversion occurs is called the Threshold Voltage (Vt).  A p-depletion layer have more holes than p-substrate since its electrons have been pushed into the inversion layer.  Does not conduct when Vgs<Vt (Cut-off).

© Digital Integrated Circuits 2nd Devices Enhancement NMOS V

© Digital Integrated Circuits 2nd Devices Enhancement NMOS - VI  When Vgs>Vt, the inversion layer (n channel) becomes thicker.  The horizontal electrical field due to Vds moves electrons from the source to the drain through the channel.  If Vds=0, the channel is formed but not conduct.

© Digital Integrated Circuits 2nd Devices Case when Vds=0

© Digital Integrated Circuits 2nd Devices Linear Region

© Digital Integrated Circuits 2nd Devices Linear Region - II  When Vgs>Vt and Vgd>Vt, the inversion layer increases in thickness and conduction increases.  The reason is that there are non-zero inversion layer at both source and drain (our previous analysis works for both Vgs and Vgd).This is called linear region.  Vgd>Vt means that Vgd=Vgs-Vds>=Vt, i.e., Vds<=Vgs-Vt  Vds>0  Ids depends on Vg, Vgs, Vds and Vt.

© Digital Integrated Circuits 2nd Devices Saturation Region

© Digital Integrated Circuits 2nd Devices Saturation Region - II  When Vgs>Vt and Vgd<Vt, we have non- zero inversion layer at source but zero inversion layer at drain.  Inversion layer is said to be pinched off. This is called the saturation region.  Vgd Vgs-Vt.  Electrons leaves the channel and moves to drain terminal through depletion region.

© Digital Integrated Circuits 2nd Devices Saturation Region - III  In saturation region, the voltage difference over the channel remains at Vgs-Vt. This is because if Vds=Vgs-Vt, the inversion layer is barely pinched off at the drain (since then Vgd=Vt). If Vds>Vgs-Vt, the channel is pinched off somewhere between the drain and source ends. Thus, the voltage applied across the channel is Vgs-Vt.  As a result, Ids depends on Vgs in this region, so we cannot keep raising Vds to get better conduction.

© Digital Integrated Circuits 2nd Devices Summary  Three regions of conduction  Cut-off: 0<Vgs<Vt  Linear: 0<Vds<Vgs-Vt  Saturation: 0<Vgs-Vt<Vds  Vt depends on gate and insulator materials, thickness of insulators and so forth – process dependant factors, and Vsb and temperature – operational factors.

© Digital Integrated Circuits 2nd Devices Analysis (for linear region)

© Digital Integrated Circuits 2nd Devices Analysis - II  Denote by V(x) the voltage at a point x along the channel. The gate-to-point voltage is Vgs-V(x). Since it needs to be > Vt for every point along the channel, the charge per unit cross section area at x is  Cox is the capacitance per unit, which is where is a constant called the permittivity of the gate oxide and tox is the thickness of gate oxide.

© Digital Integrated Circuits 2nd Devices Analysis - III  Gate width W, so the total charge is QW.  I=QW/t=QWv, v being velocity of carrier.  Given surface mobility  of electrons, which depends on process, an empirical formula for v is  We have  Integrate x from 0 to L, we have  For saturation region, replace Vds by Vgs- Vt, we have. It does not depend on Vds. 1 W 1 Q I

© Digital Integrated Circuits 2nd Devices Effective Channel Length/Width is due to lateral diffusion of the source and drain junctions under the gate

© Digital Integrated Circuits 2nd Devices Channel Length Modulation  In saturation region, current is actually weakly depends on Vds. This is because that the larger Vds is, the closer the pinch- is to the source. Since electrons flow through depletion layer to move to drain in saturation region, this means a long trip. The current value is actually  is empirically determined. Usually it is <0.02/Vds.

© Digital Integrated Circuits 2nd Devices Summary - II  Three regions of conduction  Cut-off: 0<Vgs<Vt, I=0  Linear: 0<Vds<Vgs-Vt,  Saturation: 0<Vgs-Vt<Vds

© Digital Integrated Circuits 2nd Devices PMOS

© Digital Integrated Circuits 2nd Devices PMOS - II  Dual of NMOS  Three regions of conduction  Cut-off: 0>Vgs>Vt  Linear: 0>Vds>Vgs-Vt  Saturation: 0>Vgs-Vt>Vds  Current computation is the same as NMOS except that the polarities of all voltages and currents are reversed.  Mobility of holes u in PMOS is usually half of the mobility of electronics in NMOS due to process technology.

© Digital Integrated Circuits 2nd Devices I-V characteristics (different Vt)

© Digital Integrated Circuits 2nd Devices I-V Characteristics II

© Digital Integrated Circuits 2nd Devices Threshold Voltage and Body Effect  Since gate and substrate form the plates of a capacitor, a strong enough inversion layer needs sufficient amount of voltage difference, i.e., Vgs=Vt.  If we decrease the bulk/substrate voltage Vb, more charge is needed on the lower plate to counteract it.  Vgs needs to be above the normal Vt in order to form the same inversion layer as before without bulk voltage decrease. You can treat it as increasing Vt.  Make the circuit run slower.  It is called Body Effect. Try to avoid it.  where is called the body-effect coefficient and V t0 is the threshold voltage when Vsb=0.

© Digital Integrated Circuits 2nd Devices Threshold Voltage and Body Effect

© Digital Integrated Circuits 2nd Devices Short Channel Effects  is true for long channel.  The depletion layer/electron move under the gate is assumed to be caused entirely by vertical field, i.e.,  Near source and drain, there is also depleted region due to horizontal electrical field (Vd,Vs). So the region below gate is already partially depleted.  Device actually conducts with smaller Vt.  If the channel is very short, effect is significant, which make the device hard to control.  In practice, L>= Lmin.

© Digital Integrated Circuits 2nd Devices Short Channel Effect - II

© Digital Integrated Circuits 2nd Devices Sub-threshold conduction (Leakage)  Vgs<Vt, cut-off and I=0. Not true.  In practice, for Vgs<Vt,  I is exponentially dependent on Vgs. I d0 and n are experimentally determined, k is Boltzmann’s constant and T is temperature.  Source of standby power consumption in portable devices.  Some extremely low-power circuits use sub-threshold conduction, e.g., digital watch.

© Digital Integrated Circuits 2nd Devices Transistor Equivalent Resistance  In linear region, R=V/I, so  In saturation region, the voltage applied across the channel is Vgs-Vt. Thus,  Roughly speaking, channel resistance inversely depends on W since

© Digital Integrated Circuits 2nd Devices Transistor Resistance - II  Larger gate width (larger gate area) -> smaller resistance -> device runs faster  This means that power/area increases with delay decreases. A lot of power-delay tradeoff like this.

© Digital Integrated Circuits 2nd Devices Transistor Resistance - III

© Digital Integrated Circuits 2nd Devices Transistor Capacitance Gate Capacitance = Channel Capacitance + Overlap Capacitance

© Digital Integrated Circuits 2nd Devices Overlap Capacitance t ox n + n + Cross section L Gate oxide x d x d L d Polysilicon gate Top view Source n + Drain n + W Overlap capacitance=2Cox Xd W

© Digital Integrated Circuits 2nd Devices Channel Capacitance Cut-off ResistiveSaturation Larger gate width -> Larger capacitance

© Digital Integrated Circuits 2nd Devices Measuring the Gate Cap i=CdV/dt, so C=idt/dV

© Digital Integrated Circuits 2nd Devices In Standard Cell Library  A gate type has multiple gate sizes (widths)  Larger gate width means larger gate capacitance and smaller driving resistance.  Thus, for a gate type, we have a variety of transistors with different capacitance and resistance tradeoff.  Larger width means larger capacitance and thus larger power due to charging and uncharging the capacitance.  Usually, larger width transistor has smaller delay.

© Digital Integrated Circuits 2nd Devices Technology Scaling  Devices scale to smaller dimensions with advancing technology.  A scaling factor S describes the ratio of dimension between the old technology and the new technology. In practice, S=

© Digital Integrated Circuits 2nd Devices Technology Scaling - II  In practice, it is not feasible to scale voltage since different ICs in the system may have different Vdd. This may require extremely complex additional circuits. We can only allow very few different levels of Vdd.  In technology scaling, we often have fixed voltage scaling model.  W,L,tox scales down by 1/S  Vdd, Vt unchanged  Area scales down by 1/S 2  Cox scales up by S due to tox  Gate capacitance = CoxWL scales down by 1/S  scales up by S  Linear and saturation region current scales up by S  Current density scales up by S 3  P=Vdd*I, power density scales up by S 3  Power consumption is a major design issue

© Digital Integrated Circuits 2nd Devices Summary  NMOS  Cut-Off, Linear and Saturation Regions  How to compute I  Channel length modulation, short channel effect, sub- threshold conduction  PMOS is the dual device of NMOS  I-V characteristics of MOS transistors  Resistance  Capacitance