Interrupt, again! Lin Zhong ELEC424, Fall 2010.

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Presentation transcript:

Interrupt, again! Lin Zhong ELEC424, Fall 2010

IAR EWR interrupt Enable interrupt 3

IAR EWR interrupt Interrupt handler is a special subroutine 4

16-bit address for interrupt handler routine

Registers General purpose registers – R4-R15 in MSP430F169 Special purpose registers – Program counter (PC), stack pointer (SP), status (SR), … Pipeline registers ……… …….. Controller state registers

Copyright © 2007 Elsevier 3- Finite State Machine (FSM) Consists of: –State register that Store the current state and Load the next state at the clock edge –Combinational logic that Computes the next state Computes the outputs

Copyright © 2007 Elsevier 3- Finite State Machines (FSMs) Next state is determined by the current state and the inputs Two types of finite state machines differ in the output logic: –Moore FSM: outputs depend only on the current state –Mealy FSM: outputs depend on the current state and the inputs

Copyright © 2007 Elsevier 3- State Transition Diagrams Mealy FSM: arcs indicate input/output

Processor controller: a hierarchical FSM as a state can be a FSM too