1. EEL 3705 / 3705L Digital Logic Design
Spring 2007 Instructor: Dr. Michael Frank Module #15: Finite-State Machine Design (Thanks to Dr. Perry for some slides)

2. Dr. Perry’s Slides
Following are some old slides by Dr. Perry on Finite State Machines, left over from previous semesters…

3. Finite State Machine (FSM)
General Models

4. Moore FSM General Block Diagram
Next
State
Present
State
Output Vector
Input Vector
Clock
Feedback
Path
Reset
CL= Combinational Logic Cloud
Reg= D Registers

5. Moore FSM State Equations
Next
State
Present
State
Output Vector
Input Vector
Clock
Feedback
Path
Reset
State Equations

6. Mealy FSM Block Diagram and State Equations
Next
State
Present
State
Input Vector
Output Vector
Feedback
Path
Output Y is also a function
of input X

7. Mealy-Moore FSM Block Diagram and State Equations
Present State
Next State
Input Vector
Mealy Outputs
Moore Outputs

8. State Diagrams

9. State Bubble

10. State Bubble Example State name = S0 State value = 00
Conditional
Transition
Unconditional
Transition
State name = S0
State value = 00
Y = 0 for this state
We leave this state if upn=1,
We remain in this state if upn=0

11. FSM Examples

12. Example– 2-bit Up Counter
State Diagram
Clock is implied

13. Example – 2-bit Up Counter
State Table
State Value Assignment
Let
S0 = 00
S1 = 01
S2 = 10
S3 = 11 ps ns y S0 S1 S2 1 S3 2 3
Output Vector
Let S0 = reset state

14. Example – 2-bit Up Counter
Truth Table
ps1
ps0
ns1
ns0 y1 y0 1

15. Example – 2-bit Up Counter
Excitation Equations

16. Moore FSM State Equations Next State Present State Output Vector
Input Vector
Clock
Feedback
Path
Reset
State Equations

17. Logic Diagram Reg Block F Logic Y Vector H Logic
No X Vector in this Example
No H Logic needed

18. Logic Diagram

19. Flash Animation

20. Example 3– 2-bit Down Counter
State Diagram
Clock is implied

21. Example – 2-bit Down Counter
State Table
Let
S0 = 00
S1 = 01
S2 = 10
S3 = 11 ps ns y S0 S3 S2 3 S1 2 1
Let S0 = reset state

22. Example – 2-bit Down Counter
Truth Table
ps1
ps0
ns1
ns0 y1 y0 1

23. Example – 2-bit Down Counter
Excitation Equations

24. Recall Moore FSM State Equations Next State Present State
Output Vector
Input Vector
Clock
Feedback
Path
Reset
State Equations

25. Logic Diagram Reg Block F Logic Y Vector H Logic
No X Vector in this Example

26. Logic Diagram

27. Example 4 – 2-bit Up/Down Counter
State Diagram

28. Example – 2-bit Up/Down Counter
State Diagram
Shorthand Notation

29. Example – 2-bit Up/Down Counter
State Table ps ns
upn y S0 S1 S3 S2 1 2 3
Let
S0 = 00
S1 = 01
S2 = 10
S3 = 11
Let S0 = reset state

30. Example – 2-bit Up/Down Counter
Truth Table
upn
ps1
ps0
ns1
ns0 y1 y0 1

31. Example – 2-bit Up/Down Counter
Excitation Equations

32. Recall Moore FSM State Equations Next State Present State
Output Vector
Input Vector
Clock
Feedback
Path
Reset
State Equations

33. Logic Diagram
Reg Block
X Vector
F Logic
Y Vector
H Logic

34. Logic Diagram

35. Example 5– 3-bit Arbitrary Counter
Design a 3-bit arbitrary counter that will count in the following sequence
3,2,3,1,2,3
If a state is not used reset it to state zero.
How may states do we have?
How many registers do we need?
How many bits do we need for Y?

36. Example 5– 3-bit Arbitrary Counter
State Diagram

37. Example – Arbitrary 3-bit Counter
State Table
Assign State Values
Let
S0 = 000
S1 = 001
S2 = 010
S3 = 011
S4 = 100
S5 = 101
S6 = 110
S7 = 111 ps ns y S0 S1 3 S2 2 S3 S4 1 S5 S6 S7
Let S0 = reset state

38. Develop Truth Table

39. Example – 2-bit Arbitrary Counter
Develop Excitation Equations -- F Logic

40. Develop Excitation Equations for Y

41. Example – 2-bit Arbitrary Counter
Excitation Equations -- H Logic

42. Recall Moore FSM State Equations Next State Present State
Output Vector
Input Vector
Clock
Feedback
Path
Reset
State Equations

43. Logic Circuit H
REG F

44. Logic Circuit

45. Simulation

46. Example 5– 2-bit Up/Down Counter with Active Low Enable and Synchronous RESET (SRESET)
State Diagram
Clock is implied

47. Example – 2-bit Up/Down Counter with Enable and SRESET
Functional Table
srn en
upn
Function d
Synchronous Reset (sreset) 1
Hold
Count Up
Count Down
Highest Level of Priority
Lowest Level of Priority

48. State Table
Srn En
upn ns d S0 1 ps
ps+1
ps -1

49. Truth Table (5 variables!!)
Although, we could design this circuit directly from the truth table
we will use design partitioning.

50. Moore FSM Architecture
Next
State
Present
State
Output Vector
Input Vector
Feedback
Path

51. to create the “new” design.
Partitioned Design
srn
We have en
Srn En ns d S0 1 PS
Count
Note, with the partitioned design we can “reuse” already designed submodules
to create the “new” design.

52. Top Level Block Diagram

53. UP/Down Logic
Logic Circuit
Symbol

54. Register Block
Symbol
Logic Circuit

55. 2 Bit 4x1 Mux
Circuit
Symbol

56. 1-bit 4x1 Mux
Logic Circuit
Symbol

57. 1-bit 2x1 Mux
Logic Circuit
Symbol

58. Top Level Block Diagram

59. Simulation

60. Example 6 – FSM Controller
State Diagram

61. Truth Table for NS
Truth Table

62. Kmaps for NS1 and NS0
NS1
NS0

63. Truth Table and Equations for Y
Recall, Moore FSM, so Y will
Not be a function of T
By Inspection

64. Logic Circuit H
REG F

65. Simulation