Atsushi Taketani 2005/06/03 VTX meeting 1 PIXEL BUS status 1.Circuit design 2.Design rule and design 3.Schedule

Atsushi Taketani 2005/06/03 VTX meeting 2 Prototype Design Two completely independent bus with two digital pilot, analog pilot, and GOL Readout Chip Sensor Pixel Bus SPIRO Digital Pilot Analog pilot GOL

Atsushi Taketani 2005/06/03 VTX meeting 3 Each Readout chip logic diagram for PHENIX PIXEL

Atsushi Taketani 2005/06/03 VTX meeting 4 Bus connection to SPIRO logic diagram for PHENIX PIXEL

Atsushi Taketani 2005/06/03 VTX meeting 5 Circuit Design A few minor change Value of bias filtering capacitor. ( larger) Number of bypass capacitor ( under discussion )

Atsushi Taketani 2005/06/03 VTX meeting 6 Design rule 70  m line width, 50  m space Through hole 50  m diameter and100  m land size. Connection pad 200  m width. Bending radius 20mm. HV bias(<100V) will be isolated from other line.

Atsushi Taketani 2005/06/03 VTX meeting 7 Dimensions Bus width 15mm. Length 10cm ( Sensor ) + 15cm(extention)

Atsushi Taketani 2005/06/03 VTX meeting 8 Layer 1 and Layer 2 Layer 3 Bus with Sensors extension connection As of May 20, I discussed with SOLITON Co.

Atsushi Taketani 2005/06/03 VTX meeting 9 Layout Several iteration of design Final review in next week ( June 9 th )

Atsushi Taketani 2005/06/03 VTX meeting 10 Schedule Finalize layout in next week. Cu bus fabrication in a month Al bus for 2 month after Cu bus. After finalize Bus, we will start to design Cu extender with layout engineer.