1. Columbia University IN THE CITY OF NEW YORK ROC3' / preproduction ROC Design Status E.J. Mannel StriPixel Review October 1, 2008

2. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 2 Strip Ladder Conceptual Design (Details to follow) ROC BUS Ladder Data Transfer Board FEM DCM Top View of ladder Bottom View of Ladder RCC Carbon Fiber Stave and Cooling (Light Blue) Optical Fiber BUS

3. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 3 Strip Read Out Card (ROC) Strip ROC consists of: StriPixel Silicon sensor 768 (6*128) X channels 768 (6*128) U channels split equally in to 3cm x 3cm region 12 SVX4 readout chips Passive component for SVX4 chips Interconnect with RCC module

4. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 4 interconnect ROC Module-Concept Stripixel Sensor svx4 connector Routing of SVX4 Control/Data Signals Location of Passive components

5. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 5 Readout Control Chip (RCC) Module Connects to the ROC- 1 RCC per ROC Contains Rad-Hard Readout Control Chip (RCC)- Custom ASIC or FPGA Controls read out of the 12 SVX4 chips on ROC Multiplexes data onto readout bus Translates/passes LVDS signals to the SVX4s Located on back side of strip ladder. Has passive components for power filtering. Connects to Ladder Data Transfer Board (LDTB) via Ladder Bus Flex circuit construction

6. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 6 RCC Module-Concept ROC Connector ROC Connector Bus Connector RCC

7. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 7 Ladder Bus Connects multiple (5/6) RCC modules to Ladder Data transfer Board (LDTB) Flex Circuit construction Mounted on bottom of ladder, extending into Big-Wheel Region. No active components Possibly passive components for LVDS termination (Details to be worked out)

8. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 8 Ladder Data Transfer Board (LDTB) Located in Big-Wheel Region of VTX Rad-Tolerant FPGA Translates the LVDS Serial (SERDES) Strips channel numbers from the SVX4 data Receives/transmits data from/to the FEM via optical fiber BCO-Mode Bits-Slow control data Power regulation for ROC/RCC modules Rigid-Flex board design

9. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 9 Strip Front End Module (FEM) Receives/Sends optical data from/to LDTB Data reduction and reformatting: Real time pedestal subtraction Zero Suppression Adds PHENIX standard data headers and tails Optical interface to DCM2 Optical interface with GTM Sends BCO/Mode bits to LDTB Interface with slow control system

10. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 10 Strip Ladder Conceptual Design ROC BUS Ladder Data Transfer Board FEM DCM Top View of ladder Bottom View of Ladder RCC Carbon Fiber Stave and Cooling (Light Blue) Optical Fiber BUS

11. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 11 ROC2 First attempt to place ReadOut Card (ROC) in top of stripixel sensor Observed pedestal shifts attributed to capacitive coupling in the sensor and poor ground plane design Internal review of the ROC2 in July 2007 Recommendations led to ROC3 design Rachid's presentation has shown results from the ROC3 module

12. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 12 ROC3 Review Recommendations: Move readout chips to side of sensor Improve ground planes. Optimization of board stackup Not intended as a ladder ROC First modules available early 2008 Used successfully in the FNAL Beam Test (FNAL-T984) effort in the summer of 2008 Lessons learned were used for ROC3' design

13. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 13 ROC3' Minimal redesign of ROC3 to improve ease and yield of the fabrication and assembly of the ROC module Verify reproducibility of ROC3 performance Study the impact of changes in the overall board thickness and thickness of copper layers Study the impact of moving/reducing passive components on the ROC

14. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 14 ROC3' Design Maintain the same stack up as ROC3 1)Analog ground/ Components 2)Analog Power/ Digital Ground 3)Digital Signal 4)Digital Power/Digital Signal 5)Digital Ground Wire bond SVX4 I/O pads directly to inner layer traces Requires a milled opening or cavity through first two layers of board All components on top of the ROC

15. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 15 ROC3' Design Changes Increased size of wire bond pads where possible Relocated passive components to improve wire bonding if possible Increase size of opening to access inner layer for wire bonding of SVX4 I/O connections Reduce overall board thickness Produce board with both ½ oz and ¼ oz copper layers

16. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 16 ROC3' Summary ROC3' is a success: Analog performance matched or exceeded ROC3 performance (Rachid's Talk) Easier to fabricate (Hughes Circuits) Easier to assemble (Hughes Circuits/BNL- Instrumentation/SiDet) Thinner boards (overall/Cu thickness) perform well Will reduce the overall radiation thickness of the strip ladder

17. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 17 ROC3' Summary Still some fabrication and assembly issues to be addressed: Attachment process of the bias plane to the ROC still needs improvement. Opening to inner layers of ROC for wire bonding of SVX4 still difficult. Clearances still an issue: bond pad contamination (solder, flux, etc.) ¼ oz Cu version had yield problems. ROC3' lessons lead to preproduction ROC design improvements

18. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 18 preproduction ROC (ppROC) Goals Maintains or surpasses the ROC3/ROC3' performance. Meets or exceeds the baseline design specifications: overall dimensions. radiation length. Increasing the yield and reducing the cost. Not adversely effecting the VTX installation schedule.

19. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 19 ppROC Design Discussions with over the last month: VTX group to discuss global strip ladder design Catalyst Microtech, Austin TX. Wire Bonding Company Hughes Circuits, San Marcos CA Board Manufacturer/Assembler HYTEC, Los Alamos NM VTX/FVTX Engineering firm

20. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 20 Discussion Summary Suggestions: Increase die pad size for SVX4 Solder, not glue, SVX4 to ROC Increase wire bond pad size Passive components on bottom, not top Increase keep out space around bond pads Eliminate wire bonding to inner layer of ROC Aluminum wire bonding is better then gold Larger clearances/traces for improved yield

21. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 21 Discussion Summary Cont.... Place ROC-RCC connection on bottom of ROC Design staves with no opening for bottom mounted components Use stave design similar to ATLAS design Glue bus to bottom of stave Use some type of alignment pins to insure alignment of ROC/RCC/Bus during assembly process. Recommendations playing a leading role in design of the ppROC

22. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 22 ROC3' Passive Component Issue High density of components between SVX4s: Requires stacking of some components- 0201 on 0402 Interference with wire- bonding Tight tolerance: 3 mil clearance Chance that solder mask will not flow properly

23. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 23 ppROC Passive Component Solution Move components to back side: More area available for components No need to stack components No issues with pad contamination Allows repositioning and enlargening of bond pads Yellow top layer Magenta inner layers Green bottom Layer

24. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 24 ROC3' Bias Plane Attachment Issue Attached separately after surface mount components are attached by hand. Required due to 0201 components on the top Attachment technique results in uneven surface for svx4s and sensor Labor intensive

25. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 25 ppROC Bias Plane Attachment Solution Bias plane can be laminated on. Requires surface mount components on back side Allows use of solder balls in vias and re-flow to make electrical connection between layers. Allows placement of connections for bias voltage under the sensor Connection points should be level and not interfere with sensor or SVX4s

26. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 26 ROC3' SVX4 I/O Pad Opening Issue 12 slots milled through top 2 layers to expose inner layer bond pads Milled after board lamination. Risk of damaging inner layer (yield) Increases difficulty of wire- bonding. Wire bond pads are narrow, 4 mils

27. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 27 ppROC SVX4 I/O Pad Opening Solution Move bond pads to top layer Stagger pads to allow wider pads for bonding (not shown) Reduces problems with wire bonding Bond Pad region Traces on top

28. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 28 ROC3' Overall Flatness Issue Small amount of warpage in board Result of: Thin boards Asymmetric stack-up Very little can be done given the design-Inherent in the board design and fabrication process.

29. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 29 ROC3' ¼ Oz Copper Issues Loss of electrical connectivity on board Result of fabrication steps ¼ oz Cu =.35 mil thick Different steps can remove some of the copper Cobra step most damaging Results in loss of electrical continuity on traces

30. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 30 ppROC ¼ Oz Copper Solution ½ oz Cu on trace planes. Wider traces where possible No need for Cobra step on trace planes. part of the fabrication process Make ground and power planes ¼ oz Cu. Will reduce overall board radiation thickness

31. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 31 ppROC-RCC Connection Propose using interposer solution from Paricon Well established technology High reliability: Connection pads on RCC and ppROC are mated with PariPoser material in between. Applied force maintains connection- requires carbon fiber stiffener on ppROC and RCC Can be used for signals, power and bias connections

32. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 32 ppROC-RCC Connection Silicone insulator with vertical conduction paths Placed between pads, compression makes the connection between surfaces Alignment only of circuit boards required

33. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 33 ppROC-RCC Interconnection

34. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 34 Mechanical Board Dimensions: Wide board design is baseline (SVX4s on the side of the sensor). Maintain 80mm board width base line. Maintain 65mm board length base line Baseline dimensions can be met: ppROC-RCC connection grid on bottom of ROC No flex cable to wrap around stave Component placement is still tight

35. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 35 Mechanical Dimensions

36. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 36 ppROC Work in Progress New Schematic almost complete Changes for final ppROC-RCC connection required Move power filtering caps to the RCC ppROC layout has started, but still work to be done. New ppROC-RCC connector Changes to SVX4 die pad size Change location and size of bond pads Change bias plane connections

37. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 37 ppROC Work in Progress... Working on test board to verify ppROC-RCC interconnect- ORNL Verifying bias plane connection technique: Design test board (ORNL) Fabricate at Hughes Verify connections and flatness of technique (Hughes)

38. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 38 ppROC Schedule Layout complete in early 4Q CY-2008 First ppROCs fabricated late 4Q CY-2008 First strip modules assembled early 1Q CY- 2009 First strip modules ready for system chain test late 1Q CY-2009

39. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 39 Conclusions ROC3' performed as well as ROC3 Lessons learned from ROC3' will improve ppROC design: Ease of fabrication and assembly Result in improved yield and lower cost ppROC design will maintain baseline ladder design constaints and meet performance requirements Time line is consistent with chain test in 1Q CY 2009

40. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 40 Backup

41. Columbia University IN THE CITY OF NEW YORK 09/30/08 Eric J. Mannel mannel@nevis.columbia.edu 41 Concerns/Issues Test of removing “extra” filter caps showed widening of pedestals for some SVX4s